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Linux/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Freescale Layerscape SCFG PCIe MSI controller
  8 
  9 description: |
 10   This interrupt controller hardware is a second level interrupt controller that
 11   is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
 12   platforms. If interrupt-parent is not provided, the default parent interrupt
 13   controller will be used.
 14 
 15   Each PCIe node needs to have property msi-parent that points to
 16   MSI controller node
 17 
 18 maintainers:
 19   - Frank Li <Frank.Li@nxp.com>
 20 
 21 properties:
 22   compatible:
 23     enum:
 24       - fsl,ls1012a-msi
 25       - fsl,ls1021a-msi
 26       - fsl,ls1043a-msi
 27       - fsl,ls1043a-v1.1-msi
 28       - fsl,ls1046a-msi
 29 
 30   reg:
 31     maxItems: 1
 32 
 33   '#msi-cells':
 34     const: 1
 35 
 36   interrupts:
 37     items:
 38       - description: Shared MSI interrupt group 0
 39       - description: Shared MSI interrupt group 1
 40       - description: Shared MSI interrupt group 2
 41       - description: Shared MSI interrupt group 3
 42     minItems: 1
 43 
 44 required:
 45   - compatible
 46   - reg
 47   - msi-controller
 48   - interrupts
 49 
 50 allOf:
 51   - $ref: msi-controller.yaml
 52   - if:
 53       properties:
 54         compatible:
 55           contains:
 56             enum:
 57               - fsl,ls1046a-msi
 58     then:
 59       properties:
 60         interrupts:
 61           minItems: 4
 62     else:
 63       properties:
 64         interrupts:
 65           maxItems: 1
 66 
 67 unevaluatedProperties: false
 68 
 69 examples:
 70   - |
 71     #include <dt-bindings/interrupt-controller/arm-gic.h>
 72 
 73     interrupt-controller@1571000 {
 74         compatible = "fsl,ls1043a-msi";
 75         reg = <0x1571000 0x8>;
 76         msi-controller;
 77         #msi-cells = <1>;
 78         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 79     };

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