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Linux/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Loongson Local I/O Interrupt Controller
  8 
  9 maintainers:
 10   - Jiaxun Yang <jiaxun.yang@flygoat.com>
 11 
 12 description: |
 13   This interrupt controller is found in the Loongson-3 family of chips and
 14   Loongson-2K series chips, as the primary package interrupt controller which
 15   can route local I/O interrupt to interrupt lines of cores.
 16   Be aware of the following points.
 17   1.The Loongson-2K0500 is a single core CPU;
 18   2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
 19     need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
 20     sources respectively.
 21 
 22 allOf:
 23   - $ref: /schemas/interrupt-controller.yaml#
 24 
 25 properties:
 26   compatible:
 27     enum:
 28       - loongson,liointc-1.0
 29       - loongson,liointc-1.0a
 30       - loongson,liointc-2.0
 31 
 32   reg:
 33     minItems: 1
 34     maxItems: 3
 35 
 36   reg-names:
 37     items:
 38       - const: main
 39       - const: isr0
 40       - const: isr1
 41     minItems: 2
 42 
 43   interrupt-controller: true
 44 
 45   interrupts:
 46     description:
 47       Interrupt source of the CPU interrupts.
 48     minItems: 1
 49     maxItems: 4
 50 
 51   interrupt-names:
 52     description: List of names for the parent interrupts.
 53     items:
 54       pattern: int[0-3]
 55     minItems: 1
 56     maxItems: 4
 57 
 58   '#interrupt-cells':
 59     const: 2
 60 
 61   loongson,parent_int_map:
 62     description: |
 63       This property points how the children interrupts will be mapped into CPU
 64       interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
 65       and each bit in the cell refers to a child interrupt from 0 to 31.
 66       If a CPU interrupt line didn't connect with liointc, then keep its
 67       cell with zero.
 68     $ref: /schemas/types.yaml#/definitions/uint32-array
 69     minItems: 4
 70     maxItems: 4
 71 
 72 required:
 73   - compatible
 74   - reg
 75   - interrupts
 76   - interrupt-names
 77   - interrupt-controller
 78   - '#interrupt-cells'
 79   - loongson,parent_int_map
 80 
 81 
 82 unevaluatedProperties: false
 83 
 84 if:
 85   properties:
 86     compatible:
 87       contains:
 88         enum:
 89           - loongson,liointc-2.0
 90 
 91 then:
 92   properties:
 93     reg:
 94       minItems: 2
 95       maxItems: 3
 96 
 97   required:
 98     - reg-names
 99 
100 else:
101   properties:
102     reg:
103       maxItems: 1
104 
105 examples:
106   - |
107     iointc: interrupt-controller@3ff01400 {
108       compatible = "loongson,liointc-1.0";
109       reg = <0x3ff01400 0x64>;
110 
111       interrupt-controller;
112       #interrupt-cells = <2>;
113 
114       interrupt-parent = <&cpuintc>;
115       interrupts = <2>, <3>;
116       interrupt-names = "int0", "int1";
117 
118       loongson,parent_int_map = <0xf0ffffff>, /* int0 */
119                                 <0x0f000000>, /* int1 */
120                                 <0x00000000>, /* int2 */
121                                 <0x00000000>; /* int3 */
122 
123     };
124 
125 ...

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