1 Marvell ICU Interrupt Controller
2 --------------------------------
3
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
9 their type (NSR, SR, SEI, REI, etc).
10
11 Required properties:
12
13 - compatible: Should be "marvell,cp110-icu"
14
15 - reg: Should contain ICU registers location and length.
16
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
18 with their own compatible.
19
20 Required properties for the icu_nsr/icu_sei subnodes:
21
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
27
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
30
31 The 1st cell is the index of the interrupt in the ICU unit.
32
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
34 details.
35
36 - interrupt-controller: Identifies the node as an interrupt
37 controller.
38
39 - msi-parent: Should point to the GICP controller, the GIC extension
40 that allows to trigger interrupts using MSG memory mapped
41 transactions.
42
43 Note: each 'interrupts' property referring to any 'icu_xxx' node shall
44 have a different number within [0:206].
45
46 Example:
47
48 icu: interrupt-controller@1e0000 {
49 compatible = "marvell,cp110-icu";
50 reg = <0x1e0000 0x440>;
51
52 CP110_LABEL(icu_nsr): interrupt-controller@10 {
53 compatible = "marvell,cp110-icu-nsr";
54 reg = <0x10 0x20>;
55 #interrupt-cells = <2>;
56 interrupt-controller;
57 msi-parent = <&gicp>;
58 };
59
60 CP110_LABEL(icu_sei): interrupt-controller@50 {
61 compatible = "marvell,cp110-icu-sei";
62 reg = <0x50 0x10>;
63 #interrupt-cells = <2>;
64 interrupt-controller;
65 msi-parent = <&sei>;
66 };
67 };
68
69 node1 {
70 interrupt-parent = <&icu_nsr>;
71 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
72 };
73
74 node2 {
75 interrupt-parent = <&icu_sei>;
76 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
77 };
78
79 /* Would not work with the above nodes */
80 node3 {
81 interrupt-parent = <&icu_nsr>;
82 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
83 };
84
85 The legacy bindings were different in this way:
86
87 - #interrupt-cells: The value was 3.
88 The 1st cell was the group type of the ICU interrupt. Possible
89 group types were:
90 ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
91 ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
92 ICU_GRP_SEI (0x4) : System error interrupt
93 ICU_GRP_REI (0x5) : RAM error interrupt
94 The 2nd cell was the index of the interrupt in the ICU unit.
95 The 3rd cell was the type of the interrupt. See arm,gic.txt for
96 details.
97
98 Example:
99
100 icu: interrupt-controller@1e0000 {
101 compatible = "marvell,cp110-icu";
102 reg = <0x1e0000 0x440>;
103
104 #interrupt-cells = <3>;
105 interrupt-controller;
106 msi-parent = <&gicp>;
107 };
108
109 node1 {
110 interrupt-parent = <&icu>;
111 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
112 };
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