1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
8
9 maintainers:
10 - Marek Behún <kabel@kernel.org>
11
12 description: |
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
15
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
17
18 Provides MSI handling for the PCIe controllers.
19
20 properties:
21 compatible:
22 const: marvell,mpic
23
24 reg:
25 items:
26 - description: main registers
27 - description: per-cpu registers
28
29 interrupts:
30 items:
31 - description: |
32 Parent interrupt on platforms where MPIC is not the top-level
33 interrupt controller.
34
35 interrupt-controller: true
36
37 '#interrupt-cells':
38 const: 1
39
40 msi-controller: true
41
42 required:
43 - compatible
44 - reg
45 - interrupt-controller
46 - '#interrupt-cells'
47 - msi-controller
48
49 additionalProperties: false
50
51 examples:
52 - |
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/interrupt-controller/irq.h>
55
56 interrupt-controller@20a00 {
57 compatible = "marvell,mpic";
58 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
59 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
60 interrupt-controller;
61 #interrupt-cells = <1>;
62 msi-controller;
63 };
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