1 Marvell SEI (System Error Interrupt) Controller
2 -----------------------------------------------
3
4 Marvell SEI (System Error Interrupt) controller is an interrupt
5 aggregator. It receives interrupts from several sources and aggregates
6 them to a single interrupt line (an SPI) on the parent interrupt
7 controller.
8
9 This interrupt controller can handle up to 64 SEIs, a set comes from the
10 AP and is wired while a second set comes from the CPs by the mean of
11 MSIs.
12
13 Required properties:
14
15 - compatible: should be one of:
16 * "marvell,ap806-sei"
17 - reg: SEI registers location and length.
18 - interrupts: identifies the parent IRQ that will be triggered.
19 - #interrupt-cells: number of cells to define an SEI wired interrupt
20 coming from the AP, should be 1. The cell is the IRQ
21 number.
22 - interrupt-controller: identifies the node as an interrupt controller
23 for AP interrupts.
24 - msi-controller: identifies the node as an MSI controller for the CPs
25 interrupts.
26
27 Example:
28
29 sei: interrupt-controller@3f0200 {
30 compatible = "marvell,ap806-sei";
31 reg = <0x3f0200 0x40>;
32 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
33 #interrupt-cells = <1>;
34 interrupt-controller;
35 msi-controller;
36 };
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