1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MStar Interrupt Controller
8
9 maintainers:
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
11
12 description: |+
13 MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
14 interrupt controllers that routes interrupts to the GIC.
15
16 The HW block exposes a number of interrupt controllers, each
17 can support up to 64 interrupts.
18
19 properties:
20 compatible:
21 const: mstar,mst-intc
22
23 interrupt-controller: true
24
25 "#interrupt-cells":
26 const: 3
27 description: |
28 Use the same format as specified by GIC in arm,gic.yaml.
29
30 reg:
31 maxItems: 1
32
33 mstar,irqs-map-range:
34 description: |
35 The range <start, end> of parent interrupt controller's interrupt
36 lines that are hardwired to mstar interrupt controller.
37 $ref: /schemas/types.yaml#/definitions/uint32-matrix
38 items:
39 minItems: 2
40 maxItems: 2
41
42 mstar,intc-no-eoi:
43 description:
44 Mark this controller has no End Of Interrupt(EOI) implementation.
45 type: boolean
46
47 required:
48 - compatible
49 - reg
50 - mstar,irqs-map-range
51
52 additionalProperties: false
53
54 examples:
55 - |
56 mst_intc0: interrupt-controller@1f2032d0 {
57 compatible = "mstar,mst-intc";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 interrupt-parent = <&gic>;
61 reg = <0x1f2032d0 0x30>;
62 mstar,irqs-map-range = <0 63>;
63 };
64 ...
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