1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MIPS Global Interrupt Controller
8
9 maintainers:
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
12
13 description: |
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
18
19 properties:
20 compatible:
21 const: mti,gic
22
23 "#interrupt-cells":
24 const: 3
25 description: |
26 The 1st cell is the type of interrupt: local or shared defined in the
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
29 the IRQ trigger modes, which are defined in the file
30 'dt-bindings/interrupt-controller/irq.h'.
31
32 reg:
33 description: |
34 Base address and length of the GIC registers space. If not present,
35 the base address reported by the hardware GCR_GIC_BASE will be used.
36 maxItems: 1
37
38 interrupt-controller: true
39
40 mti,reserved-cpu-vectors:
41 description: |
42 Specifies the list of CPU interrupt vectors to which the GIC may not
43 route interrupts. This property is ignored if the CPU is started in EIC
44 mode.
45 $ref: /schemas/types.yaml#/definitions/uint32-array
46 minItems: 1
47 maxItems: 6
48 uniqueItems: true
49 items:
50 minimum: 2
51 maximum: 7
52
53 mti,reserved-ipi-vectors:
54 description: |
55 Specifies the range of GIC interrupts that are reserved for IPIs.
56 It accepts two values: the 1st is the starting interrupt and the 2nd is
57 the size of the reserved range. If not specified, the driver will
58 allocate the last (2 * number of VPEs in the system).
59 $ref: /schemas/types.yaml#/definitions/uint32-array
60 items:
61 - minimum: 0
62 maximum: 254
63 - minimum: 2
64 maximum: 254
65
66 timer:
67 type: object
68 description: |
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
70 timers, and a watchdog. Currently only the GIC Timer is supported.
71 properties:
72 compatible:
73 const: mti,gic-timer
74
75 interrupts:
76 description: |
77 Interrupt for the GIC local timer, so normally it's suppose to be of
78 <GIC_LOCAL X IRQ_TYPE_NONE> format.
79 maxItems: 1
80
81 clocks:
82 maxItems: 1
83
84 clock-frequency: true
85
86 required:
87 - compatible
88 - interrupts
89
90 oneOf:
91 - required:
92 - clocks
93 - required:
94 - clock-frequency
95
96 additionalProperties: false
97
98 additionalProperties: false
99
100 required:
101 - compatible
102 - "#interrupt-cells"
103 - interrupt-controller
104
105 examples:
106 - |
107 #include <dt-bindings/interrupt-controller/mips-gic.h>
108 #include <dt-bindings/interrupt-controller/irq.h>
109
110 interrupt-controller@1bdc0000 {
111 compatible = "mti,gic";
112 reg = <0x1bdc0000 0x20000>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
115 mti,reserved-cpu-vectors = <7>;
116 mti,reserved-ipi-vectors = <40 8>;
117
118 timer {
119 compatible = "mti,gic-timer";
120 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
121 clock-frequency = <50000000>;
122 };
123 };
124 - |
125 #include <dt-bindings/interrupt-controller/mips-gic.h>
126 #include <dt-bindings/interrupt-controller/irq.h>
127
128 interrupt-controller@1bdc0000 {
129 compatible = "mti,gic";
130 reg = <0x1bdc0000 0x20000>;
131 interrupt-controller;
132 #interrupt-cells = <3>;
133
134 timer {
135 compatible = "mti,gic-timer";
136 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
137 clocks = <&cpu_pll>;
138 };
139 };
140 - |
141 interrupt-controller {
142 compatible = "mti,gic";
143 interrupt-controller;
144 #interrupt-cells = <3>;
145 };
146 ...
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