1 NVIDIA Legacy Interrupt Controller
2
3 All Tegra SoCs contain a legacy interrupt controller that routes
4 interrupts to the GIC, and also serves as a wakeup source. It is also
5 referred to as "ictlr", hence the name of the binding.
6
7 The HW block exposes a number of interrupt controllers, each
8 implementing a set of 32 interrupts.
9
10 Required properties:
11
12 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
13 subsequent SoCs remained backwards-compatible with Tegra30, so on
14 Tegra generations later than Tegra30 the compatible value should
15 include "nvidia,tegra30-ictlr".
16 - reg : Specifies base physical address and size of the registers.
17 Each controller must be described separately (Tegra20 has 4 of them,
18 whereas Tegra30 and later have 5).
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
21 interrupt source. The value must be 3.
22
23 Notes:
24
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
28 are explicitly forbidden.
29
30 Example:
31
32 ictlr: interrupt-controller@60004000 {
33 compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
34 reg = <0x60004000 64>,
35 <0x60004100 64>,
36 <0x60004200 64>,
37 <0x60004300 64>;
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 interrupt-parent = <&intc>;
41 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.