1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
8
9 maintainers:
10 - Anup Patel <anup@brainfault.org>
11
12 description:
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
17
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
19 interrupt sources connect to the root APLIC domain and a parent APLIC
20 domain can delegate interrupt sources to it's child APLIC domains. There
21 is one device tree node for each APLIC domain.
22
23 allOf:
24 - $ref: /schemas/interrupt-controller.yaml#
25
26 properties:
27 compatible:
28 items:
29 - enum:
30 - qemu,aplic
31 - const: riscv,aplic
32
33 reg:
34 maxItems: 1
35
36 interrupt-controller: true
37
38 "#interrupt-cells":
39 const: 2
40
41 interrupts-extended:
42 minItems: 1
43 maxItems: 16384
44 description:
45 Given APLIC domain directly injects external interrupts to a set of
46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
47 node, which has a CPU node (i.e. RISC-V HART) as parent.
48
49 msi-parent:
50 description:
51 Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
52 message signaled interrupt controller (IMSIC). If both "msi-parent" and
53 "interrupts-extended" properties are present then it means the APLIC
54 domain supports both MSI mode and Direct mode in HW. In this case, the
55 APLIC driver has to choose between MSI mode or Direct mode.
56
57 riscv,num-sources:
58 $ref: /schemas/types.yaml#/definitions/uint32
59 minimum: 1
60 maximum: 1023
61 description:
62 Specifies the number of wired interrupt sources supported by this
63 APLIC domain.
64
65 riscv,children:
66 $ref: /schemas/types.yaml#/definitions/phandle-array
67 minItems: 1
68 maxItems: 1024
69 items:
70 maxItems: 1
71 description:
72 A list of child APLIC domains for the given APLIC domain. Each child
73 APLIC domain is assigned a child index in increasing order, with the
74 first child APLIC domain assigned child index 0. The APLIC domain child
75 index is used by firmware to delegate interrupts from the given APLIC
76 domain to a particular child APLIC domain.
77
78 riscv,delegation:
79 $ref: /schemas/types.yaml#/definitions/phandle-array
80 minItems: 1
81 maxItems: 1024
82 items:
83 items:
84 - description: child APLIC domain phandle
85 - description: first interrupt number of the parent APLIC domain (inclusive)
86 - description: last interrupt number of the parent APLIC domain (inclusive)
87 description:
88 A interrupt delegation list where each entry is a triple consisting
89 of child APLIC domain phandle, first interrupt number of the parent
90 APLIC domain, and last interrupt number of the parent APLIC domain.
91 Firmware must configure interrupt delegation registers based on
92 interrupt delegation list.
93
94 dependencies:
95 riscv,delegation: [ "riscv,children" ]
96
97 required:
98 - compatible
99 - reg
100 - interrupt-controller
101 - "#interrupt-cells"
102 - riscv,num-sources
103
104 anyOf:
105 - required:
106 - interrupts-extended
107 - required:
108 - msi-parent
109
110 unevaluatedProperties: false
111
112 examples:
113 - |
114 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
115
116 interrupt-controller@c000000 {
117 compatible = "qemu,aplic", "riscv,aplic";
118 interrupts-extended = <&cpu1_intc 11>,
119 <&cpu2_intc 11>,
120 <&cpu3_intc 11>,
121 <&cpu4_intc 11>;
122 reg = <0xc000000 0x4080>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 riscv,num-sources = <63>;
126 riscv,children = <&aplic1>, <&aplic2>;
127 riscv,delegation = <&aplic1 1 63>;
128 };
129
130 aplic1: interrupt-controller@d000000 {
131 compatible = "qemu,aplic", "riscv,aplic";
132 interrupts-extended = <&cpu1_intc 9>,
133 <&cpu2_intc 9>;
134 reg = <0xd000000 0x4080>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 riscv,num-sources = <63>;
138 };
139
140 aplic2: interrupt-controller@e000000 {
141 compatible = "qemu,aplic", "riscv,aplic";
142 interrupts-extended = <&cpu3_intc 9>,
143 <&cpu4_intc 9>;
144 reg = <0xe000000 0x4080>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 riscv,num-sources = <63>;
148 };
149
150 - |
151 // Example 2 (APLIC domains forwarding interrupts as MSIs):
152
153 interrupt-controller@c000000 {
154 compatible = "qemu,aplic", "riscv,aplic";
155 msi-parent = <&imsic_mlevel>;
156 reg = <0xc000000 0x4000>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 riscv,num-sources = <63>;
160 riscv,children = <&aplic3>;
161 riscv,delegation = <&aplic3 1 63>;
162 };
163
164 aplic3: interrupt-controller@d000000 {
165 compatible = "qemu,aplic", "riscv,aplic";
166 msi-parent = <&imsic_slevel>;
167 reg = <0xd000000 0x4000>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 riscv,num-sources = <63>;
171 };
172 ...
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