1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
8
9 description:
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
12 software. Some of these CSRs are used to control local interrupts connected
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
15
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
17 attached to every HLIC namely software interrupts, the timer interrupt, and
18 external interrupts. Software interrupts are used to send IPIs between
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
21 and CSR reads. External interrupts connect all other device interrupts to
22 the HLIC, which are routed via the platform-level interrupt controller
23 (PLIC).
24
25 All RISC-V systems that conform to the supervisor ISA specification are
26 required to have a HLIC with these three interrupt sources present. Since
27 the interrupt map is defined by the ISA it's not listed in the HLIC's device
28 tree entry, though external interrupt controllers (like the PLIC, for
29 example) will need to define how their interrupts map to the relevant HLICs.
30 This means a PLIC interrupt property will typically list the HLICs for all
31 present HARTs in the system.
32
33 maintainers:
34 - Palmer Dabbelt <palmer@dabbelt.com>
35 - Paul Walmsley <paul.walmsley@sifive.com>
36
37 properties:
38 compatible:
39 oneOf:
40 - items:
41 - const: andestech,cpu-intc
42 - const: riscv,cpu-intc
43 - const: riscv,cpu-intc
44
45 interrupt-controller: true
46
47 '#interrupt-cells':
48 const: 1
49 description: |
50 The interrupt sources are defined by the RISC-V supervisor ISA manual,
51 with only the following three interrupts being defined for
52 supervisor mode:
53 - Source 1 is the supervisor software interrupt, which can be sent by
54 an SBI call and is reserved for use by software.
55 - Source 5 is the supervisor timer interrupt, which can be configured
56 by SBI calls and implements a one-shot timer.
57 - Source 9 is the supervisor external interrupt, which chains to all
58 other device interrupts.
59
60 required:
61 - compatible
62 - '#interrupt-cells'
63 - interrupt-controller
64
65 additionalProperties: false
66
67 examples:
68 - |
69 interrupt-controller {
70 #interrupt-cells = <1>;
71 compatible = "riscv,cpu-intc";
72 interrupt-controller;
73 };
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