1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
2
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
6 controller in some SoCs, e.g. Hisilicon SD5203.
7
8 Required properties:
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
11 region starting with ENABLE_LOW register
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
14
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
17
18 The interrupt sources map to the corresponding bits in the interrupt
19 registers, i.e.
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
22 - 32 maps to bit 0 of high interrupts,
23 - 33 maps to bit 1 of high interrupts,
24 - (optional) fast interrupts start at 64.
25
26 Example:
27 /* dw_apb_ictl is used as secondary interrupt controller */
28 aic: interrupt-controller@3000 {
29 compatible = "snps,dw-apb-ictl";
30 reg = <0x3000 0xc00>;
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 interrupt-parent = <&gic>;
34 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
35 };
36
37 /* dw_apb_ictl is used as primary interrupt controller */
38 vic: interrupt-controller@10130000 {
39 compatible = "snps,dw-apb-ictl";
40 reg = <0x10130000 0x1000>;
41 interrupt-controller;
42 #interrupt-cells = <1>;
43 };
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