1 Keystone 2 IRQ controller IP
2
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
6 analyzing SRCCx bits in IPCARx registers. This is one of the component
7 used by the IPC mechanism used on Keystone SOCs.
8
9 Required Properties:
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
12 access device control registers and the offset inside
13 device control registers range.
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
16 source should be 1.
17 - interrupts: interrupt reference to primary interrupt controller
18
19 Please refer to interrupts.txt in this directory for details of the common
20 Interrupt Controllers bindings used by client devices.
21
22 Example:
23 kirq0: keystone_irq0@26202a0 {
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
26 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
27 interrupt-controller;
28 #interrupt-cells = <1>;
29 };
30
31 dsp0: dsp0 {
32 compatible = "linux,rproc-user";
33 ...
34 interrupt-parent = <&kirq0>;
35 interrupts = <10 2>;
36 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.