1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ARM SMMUv3 Architecture Implementation
8
9 maintainers:
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
12
13 description: |+
14 The SMMUv3 architecture is a significant departure from previous
15 revisions, replacing the MMIO register interface with in-memory command
16 and event queues and adding support for the ATS and PRI components of
17 the PCIe specification.
18
19 properties:
20 $nodename:
21 pattern: "^iommu@[0-9a-f]*"
22 compatible:
23 const: arm,smmu-v3
24
25 reg:
26 maxItems: 1
27
28 interrupts:
29 minItems: 1
30 maxItems: 4
31
32 interrupt-names:
33 oneOf:
34 - const: combined
35 description:
36 The combined interrupt is optional, and should only be provided if the
37 hardware supports just a single, combined interrupt line.
38 If provided, then the combined interrupt will be used in preference to
39 any others.
40 - minItems: 1
41 items:
42 enum:
43 - eventq # Event Queue not empty
44 - gerror # Global Error activated
45 - cmdq-sync # CMD_SYNC complete
46 - priq # PRI Queue not empty
47
48 '#iommu-cells':
49 const: 1
50
51 dma-coherent:
52 description: |
53 Present if page table walks made by the SMMU are cache coherent with the
54 CPU.
55
56 NOTE: this only applies to the SMMU itself, not masters connected
57 upstream of the SMMU.
58
59 msi-parent: true
60
61 hisilicon,broken-prefetch-cmd:
62 type: boolean
63 description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
64
65 cavium,cn9900-broken-page1-regspace:
66 type: boolean
67 description:
68 Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
69 register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
70 doesn't support SMMU page1 register space.
71
72 required:
73 - compatible
74 - reg
75 - '#iommu-cells'
76
77 additionalProperties: false
78
79 examples:
80 - |+
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/interrupt-controller/irq.h>
83
84 iommu@2b400000 {
85 compatible = "arm,smmu-v3";
86 reg = <0x2b400000 0x20000>;
87 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
88 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
89 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
90 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
91 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
92 dma-coherent;
93 #iommu-cells = <1>;
94 msi-parent = <&its 0xff0000>;
95 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.