1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
8
9 maintainers:
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12 description:
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
15 addressing scheme called protocol, client and signal. For example, consider an
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
17 Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18 a case, the client would be Modem (client-id is 2) and the signal would be
19 SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21 for the list of such IDs.
22
23 properties:
24 compatible:
25 items:
26 - enum:
27 - qcom,qcs8300-ipcc
28 - qcom,qdu1000-ipcc
29 - qcom,sa8255p-ipcc
30 - qcom,sa8775p-ipcc
31 - qcom,sc7280-ipcc
32 - qcom,sc8280xp-ipcc
33 - qcom,sdx75-ipcc
34 - qcom,sm6350-ipcc
35 - qcom,sm6375-ipcc
36 - qcom,sm8250-ipcc
37 - qcom,sm8350-ipcc
38 - qcom,sm8450-ipcc
39 - qcom,sm8550-ipcc
40 - qcom,sm8650-ipcc
41 - qcom,x1e80100-ipcc
42 - const: qcom,ipcc
43
44 reg:
45 maxItems: 1
46
47 interrupts:
48 maxItems: 1
49
50 interrupt-controller: true
51
52 "#interrupt-cells":
53 const: 3
54 description:
55 The first cell is the client-id, the second cell is the signal-id and the
56 third cell is the interrupt type.
57
58 "#mbox-cells":
59 const: 2
60 description:
61 The first cell is the client-id, and the second cell is the signal-id.
62
63 required:
64 - compatible
65 - reg
66 - interrupts
67 - interrupt-controller
68 - "#interrupt-cells"
69 - "#mbox-cells"
70
71 additionalProperties: false
72
73 examples:
74 - |
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 #include <dt-bindings/mailbox/qcom-ipcc.h>
77
78 mailbox@408000 {
79 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
80 reg = <0x408000 0x1000>;
81 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-controller;
83 #interrupt-cells = <3>;
84 #mbox-cells = <2>;
85 };
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