1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: STMicroelectronics STM32 IPC controller
8
9 description:
10 The IPCC block provides a non blocking signaling mechanism to post and
11 retrieve messages in an atomic way between two processors.
12 It provides the signaling for N bidirectionnal channels. The number of
13 channels (N) can be read from a dedicated register.
14
15 maintainers:
16 - Fabien Dessenne <fabien.dessenne@foss.st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
18
19 properties:
20 compatible:
21 const: st,stm32mp1-ipcc
22
23 reg:
24 maxItems: 1
25
26 clocks:
27 maxItems: 1
28
29 interrupts:
30 items:
31 - description: rx channel occupied
32 - description: tx channel free
33
34 interrupt-names:
35 items:
36 - const: rx
37 - const: tx
38
39 wakeup-source: true
40
41 "#mbox-cells":
42 const: 1
43
44 st,proc-id:
45 description: Processor id using the mailbox (0 or 1)
46 $ref: /schemas/types.yaml#/definitions/uint32
47 enum: [0, 1]
48
49 required:
50 - compatible
51 - reg
52 - st,proc-id
53 - clocks
54 - interrupt-names
55 - "#mbox-cells"
56 - interrupts
57
58 additionalProperties: false
59
60 examples:
61 - |
62 #include <dt-bindings/interrupt-controller/arm-gic.h>
63 #include <dt-bindings/clock/stm32mp1-clks.h>
64 ipcc: mailbox@4c001000 {
65 compatible = "st,stm32mp1-ipcc";
66 #mbox-cells = <1>;
67 reg = <0x4c001000 0x400>;
68 st,proc-id = <0>;
69 interrupts-extended = <&exti 61 1>,
70 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
71 interrupt-names = "rx", "tx";
72 clocks = <&rcc_clk IPCC>;
73 wakeup-source;
74 };
75
76 ...
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