1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek Media Data Path 3 HDR
8
9 maintainers:
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
12
13 description:
14 A Media Data Path 3 (MDP3) component used to perform conversion from
15 High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
16
17 properties:
18 compatible:
19 enum:
20 - mediatek,mt8195-mdp3-hdr
21
22 reg:
23 maxItems: 1
24
25 mediatek,gce-client-reg:
26 description:
27 The register of display function block to be set by gce. There are 4 arguments,
28 such as gce node, subsys id, offset and register size. The subsys id that is
29 mapping to the register of display function blocks is defined in the gce header
30 include/dt-bindings/gce/<chip>-gce.h of each chips.
31 $ref: /schemas/types.yaml#/definitions/phandle-array
32 items:
33 items:
34 - description: phandle of GCE
35 - description: GCE subsys id
36 - description: register offset
37 - description: register size
38 maxItems: 1
39
40 clocks:
41 maxItems: 1
42
43 required:
44 - compatible
45 - reg
46 - mediatek,gce-client-reg
47 - clocks
48
49 additionalProperties: false
50
51 examples:
52 - |
53 #include <dt-bindings/clock/mt8195-clk.h>
54 #include <dt-bindings/gce/mt8195-gce.h>
55
56 display@14004000 {
57 compatible = "mediatek,mt8195-mdp3-hdr";
58 reg = <0x14004000 0x1000>;
59 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
60 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
61 };
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