1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek Write DMA with Rotation
8
9 maintainers:
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
12
13 description: |
14 One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
15
16 properties:
17 compatible:
18 oneOf:
19 - enum:
20 - mediatek,mt8183-mdp3-wrot
21 - items:
22 - enum:
23 - mediatek,mt8195-mdp3-wrot
24 - const: mediatek,mt8183-mdp3-wrot
25
26 reg:
27 maxItems: 1
28
29 mediatek,gce-client-reg:
30 $ref: /schemas/types.yaml#/definitions/phandle-array
31 items:
32 items:
33 - description: phandle of GCE
34 - description: GCE subsys id
35 - description: register offset
36 - description: register size
37 description: The register of client driver can be configured by gce with
38 4 arguments defined in this property. Each GCE subsys id is mapping to
39 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
40
41 mediatek,gce-events:
42 description:
43 The event id which is mapping to the specific hardware event signal
44 to gce. The event id is defined in the gce header
45 include/dt-bindings/gce/<chip>-gce.h of each chips.
46 $ref: /schemas/types.yaml#/definitions/uint32-array
47
48 power-domains:
49 maxItems: 1
50
51 clocks:
52 minItems: 1
53
54 iommus:
55 maxItems: 1
56
57 '#dma-cells':
58 const: 1
59
60 required:
61 - compatible
62 - reg
63 - mediatek,gce-client-reg
64 - mediatek,gce-events
65 - power-domains
66 - clocks
67 - iommus
68 - '#dma-cells'
69
70 additionalProperties: false
71
72 examples:
73 - |
74 #include <dt-bindings/clock/mt8183-clk.h>
75 #include <dt-bindings/gce/mt8183-gce.h>
76 #include <dt-bindings/power/mt8183-power.h>
77 #include <dt-bindings/memory/mt8183-larb-port.h>
78
79 dma-controller@14005000 {
80 compatible = "mediatek,mt8183-mdp3-wrot";
81 reg = <0x14005000 0x1000>;
82 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
83 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
84 <CMDQ_EVENT_MDP_WROT0_EOF>;
85 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
86 clocks = <&mmsys CLK_MM_MDP_WROT0>;
87 iommus = <&iommu>;
88 #dma-cells = <1>;
89 };
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