1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: i.MX8 Image Sensing Interface
8
9 maintainers:
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11
12 description: |
13 The Image Sensing Interface (ISI) combines image processing pipelines with
14 DMA engines to process and capture frames originating from a variety of
15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
18
19 properties:
20 compatible:
21 enum:
22 - fsl,imx8mn-isi
23 - fsl,imx8mp-isi
24 - fsl,imx93-isi
25
26 reg:
27 maxItems: 1
28
29 clocks:
30 items:
31 - description: The AXI clock
32 - description: The APB clock
33 # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified
34 # as well, in case some SoCs have the ability to control them separately.
35 # This may be the case of the i.MX8[DQ]X(P)
36
37 clock-names:
38 items:
39 - const: axi
40 - const: apb
41
42 fsl,blk-ctrl:
43 $ref: /schemas/types.yaml#/definitions/phandle
44 description:
45 A phandle referencing the block control that contains the CSIS to ISI
46 gasket.
47
48 interrupts:
49 description: Processing pipeline interrupts, one per pipeline
50 minItems: 1
51 maxItems: 2
52
53 power-domains:
54 maxItems: 1
55
56 ports:
57 $ref: /schemas/graph.yaml#/properties/ports
58 description: |
59 Ports represent the Pixel Link inputs to the ISI. Their number and
60 assignment are model-dependent. Each port shall have a single endpoint.
61
62 required:
63 - compatible
64 - reg
65 - interrupts
66 - clocks
67 - clock-names
68 - fsl,blk-ctrl
69 - ports
70
71 allOf:
72 - if:
73 properties:
74 compatible:
75 contains:
76 enum:
77 - fsl,imx8mn-isi
78 - fsl,imx93-isi
79 then:
80 properties:
81 interrupts:
82 maxItems: 1
83 ports:
84 properties:
85 port@0:
86 description: MIPI CSI-2 RX
87 port@1: false
88 required:
89 - port@0
90
91 - if:
92 properties:
93 compatible:
94 contains:
95 const: fsl,imx8mp-isi
96 then:
97 properties:
98 interrupts:
99 maxItems: 2
100 ports:
101 properties:
102 port@0:
103 description: MIPI CSI-2 RX 0
104 port@1:
105 description: MIPI CSI-2 RX 1
106 required:
107 - port@0
108 - port@1
109
110 additionalProperties: false
111
112 examples:
113 - |
114 #include <dt-bindings/clock/imx8mn-clock.h>
115 #include <dt-bindings/interrupt-controller/arm-gic.h>
116 #include <dt-bindings/interrupt-controller/irq.h>
117 #include <dt-bindings/power/imx8mn-power.h>
118
119 isi@32e20000 {
120 compatible = "fsl,imx8mn-isi";
121 reg = <0x32e20000 0x100>;
122 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
124 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
125 clock-names = "axi", "apb";
126 fsl,blk-ctrl = <&disp_blk_ctrl>;
127 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
128
129 ports {
130 #address-cells = <1>;
131 #size-cells = <0>;
132
133 port@0 {
134 reg = <0>;
135 isi_in: endpoint {
136 remote-endpoint = <&mipi_csi_out>;
137 };
138 };
139 };
140 };
141
142 - |
143 #include <dt-bindings/clock/imx8mp-clock.h>
144 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 #include <dt-bindings/interrupt-controller/irq.h>
146
147 isi@32e00000 {
148 compatible = "fsl,imx8mp-isi";
149 reg = <0x32e00000 0x4000>;
150 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
153 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
154 clock-names = "axi", "apb";
155 fsl,blk-ctrl = <&media_blk_ctrl>;
156 power-domains = <&mediamix_pd>;
157
158 ports {
159 #address-cells = <1>;
160 #size-cells = <0>;
161
162 port@0 {
163 reg = <0>;
164 isi_in_0: endpoint {
165 remote-endpoint = <&mipi_csi_0_out>;
166 };
167 };
168
169 port@1 {
170 reg = <1>;
171 isi_in_1: endpoint {
172 remote-endpoint = <&mipi_csi_1_out>;
173 };
174 };
175 };
176 };
177 ...
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