1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip SoC Image Signal Processing unit v1
8
9 maintainers:
10 - Helen Koike <helen.koike@collabora.com>
11
12 description: |
13 Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
14 which contains image processing, scaling, and compression functions.
15
16 properties:
17 compatible:
18 enum:
19 - fsl,imx8mp-isp
20 - rockchip,px30-cif-isp
21 - rockchip,rk3399-cif-isp
22
23 reg:
24 maxItems: 1
25
26 interrupts:
27 minItems: 1
28 maxItems: 3
29
30 interrupt-names:
31 items:
32 - const: isp
33 - const: mi
34 - const: mipi
35
36 clocks:
37 minItems: 3
38 items:
39 # isp0 and isp1
40 - description: ISP clock (for imx8mp, clk)
41 - description: ISP AXI clock (for imx8mp, m_hclk)
42 - description: ISP AHB clock (for imx8mp, hclk)
43 # only for isp1
44 - description: ISP Pixel clock
45
46 clock-names:
47 minItems: 3
48 items:
49 # isp0 and isp1
50 - const: isp
51 - const: aclk
52 - const: hclk
53 # only for isp1
54 - const: pclk
55
56 fsl,blk-ctrl:
57 $ref: /schemas/types.yaml#/definitions/phandle-array
58 maxItems: 1
59 description:
60 A phandle to the media block control for the ISP, followed by a cell
61 containing the index of the gasket.
62
63 iommus:
64 maxItems: 1
65
66 phys:
67 maxItems: 1
68 description: phandle for the PHY port
69
70 phy-names:
71 const: dphy
72
73 power-domains:
74 maxItems: 1
75
76 ports:
77 $ref: /schemas/graph.yaml#/properties/ports
78
79 properties:
80 port@0:
81 $ref: /schemas/graph.yaml#/$defs/port-base
82 unevaluatedProperties: false
83 description: connection point for sensors at MIPI-DPHY RX0
84
85 properties:
86 endpoint:
87 $ref: video-interfaces.yaml#
88 unevaluatedProperties: false
89
90 properties:
91 data-lanes:
92 minItems: 1
93 maxItems: 4
94
95 port@1:
96 $ref: /schemas/graph.yaml#/$defs/port-base
97 unevaluatedProperties: false
98 description: connection point for input on the parallel interface
99
100 properties:
101 endpoint:
102 $ref: video-interfaces.yaml#
103 unevaluatedProperties: false
104
105 properties:
106 bus-type:
107 enum: [5, 6]
108
109 required:
110 - bus-type
111
112 anyOf:
113 - required:
114 - port@0
115 - required:
116 - port@1
117
118 required:
119 - compatible
120 - reg
121 - interrupts
122 - clocks
123 - clock-names
124 - power-domains
125 - ports
126
127 allOf:
128 - if:
129 properties:
130 compatible:
131 contains:
132 const: rockchip,rk3399-cif-isp
133 then:
134 properties:
135 clocks:
136 minItems: 3
137 maxItems: 4
138 clock-names:
139 minItems: 3
140 maxItems: 4
141
142 - if:
143 properties:
144 compatible:
145 contains:
146 const: rockchip,px30-cif-isp
147 then:
148 required:
149 - interrupt-names
150
151 - if:
152 properties:
153 compatible:
154 contains:
155 const: fsl,imx8mp-isp
156 then:
157 properties:
158 iommus: false
159 phys: false
160 phy-names: false
161 required:
162 - fsl,blk-ctrl
163 else:
164 properties:
165 fsl,blk-ctrl: false
166 required:
167 - iommus
168 - phys
169 - phy-names
170
171 additionalProperties: false
172
173 examples:
174 - |
175
176 #include <dt-bindings/clock/rk3399-cru.h>
177 #include <dt-bindings/interrupt-controller/arm-gic.h>
178 #include <dt-bindings/power/rk3399-power.h>
179
180 parent0: parent {
181 #address-cells = <2>;
182 #size-cells = <2>;
183
184 isp0: isp0@ff910000 {
185 compatible = "rockchip,rk3399-cif-isp";
186 reg = <0x0 0xff910000 0x0 0x4000>;
187 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
188 clocks = <&cru SCLK_ISP0>,
189 <&cru ACLK_ISP0_WRAPPER>,
190 <&cru HCLK_ISP0_WRAPPER>;
191 clock-names = "isp", "aclk", "hclk";
192 iommus = <&isp0_mmu>;
193 phys = <&dphy>;
194 phy-names = "dphy";
195 power-domains = <&power RK3399_PD_ISP0>;
196
197 ports {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 port@0 {
202 reg = <0>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 mipi_in_wcam: endpoint@0 {
207 reg = <0>;
208 remote-endpoint = <&wcam_out>;
209 data-lanes = <1 2>;
210 };
211
212 mipi_in_ucam: endpoint@1 {
213 reg = <1>;
214 remote-endpoint = <&ucam_out>;
215 data-lanes = <1>;
216 };
217 };
218 };
219 };
220
221 i2c7: i2c {
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 wcam: camera@36 {
226 compatible = "ovti,ov5695";
227 reg = <0x36>;
228 clocks = <&cru SCLK_TESTCLKOUT1>;
229
230 port {
231 wcam_out: endpoint {
232 remote-endpoint = <&mipi_in_wcam>;
233 data-lanes = <1 2>;
234 };
235 };
236 };
237
238 ucam: camera@3c {
239 compatible = "ovti,ov2685";
240 reg = <0x3c>;
241
242 clocks = <&cru SCLK_TESTCLKOUT1>;
243 clock-names = "xvclk";
244
245 avdd-supply = <&pp2800_cam>;
246 dovdd-supply = <&pp1800>;
247 dvdd-supply = <&pp1800>;
248
249 port {
250 ucam_out: endpoint {
251 remote-endpoint = <&mipi_in_ucam>;
252 data-lanes = <1>;
253 };
254 };
255 };
256 };
257 };
258
259 - |
260
261 #include <dt-bindings/interrupt-controller/arm-gic.h>
262 #include <dt-bindings/power/px30-power.h>
263
264 parent1: parent {
265 #address-cells = <2>;
266 #size-cells = <2>;
267
268 isp: isp@ff4a0000 {
269 compatible = "rockchip,px30-cif-isp";
270 reg = <0x0 0xff4a0000 0x0 0x8000>;
271 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-names = "isp", "mi", "mipi";
275 clocks = <&cru SCLK_ISP0>,
276 <&cru ACLK_ISP0_WRAPPER>,
277 <&cru HCLK_ISP0_WRAPPER>,
278 <&cru PCLK_ISP1_WRAPPER>;
279 clock-names = "isp", "aclk", "hclk", "pclk";
280 iommus = <&isp_mmu>;
281 phys = <&csi_dphy>;
282 phy-names = "dphy";
283 power-domains = <&power PX30_PD_VI>;
284
285 ports {
286 #address-cells = <1>;
287 #size-cells = <0>;
288
289 port@0 {
290 reg = <0>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293
294 mipi_in_ucam1: endpoint@0 {
295 reg = <0>;
296 remote-endpoint = <&ucam1_out>;
297 data-lanes = <1 2>;
298 };
299 };
300 };
301 };
302
303 i2c2: i2c {
304 #address-cells = <1>;
305 #size-cells = <0>;
306
307 ov5695: camera@36 {
308 compatible = "ovti,ov5647";
309 reg = <0x36>;
310 clocks = <&cru SCLK_CIF_OUT>;
311
312 port {
313 ucam1_out: endpoint {
314 remote-endpoint = <&mipi_in_ucam1>;
315 data-lanes = <1 2>;
316 };
317 };
318 };
319 };
320 };
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