1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-csis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
8
9 maintainers:
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12
13 properties:
14 compatible:
15 enum:
16 - samsung,s5pv210-csis
17 - samsung,exynos4210-csis
18 - samsung,exynos4212-csis
19 - samsung,exynos5250-csis
20
21 reg:
22 maxItems: 1
23
24 '#address-cells':
25 const: 1
26
27 '#size-cells':
28 const: 0
29
30 bus-width:
31 $ref: /schemas/types.yaml#/definitions/uint32
32 enum: [2, 4]
33 description:
34 Number of data lines supported.
35
36 clocks:
37 maxItems: 2
38
39 clock-names:
40 items:
41 - const: csis
42 - const: sclk_csis
43
44 clock-frequency:
45 default: 166000000
46 description:
47 The IP's main (system bus) clock frequency in Hz.
48
49 interrupts:
50 maxItems: 1
51
52 phys:
53 maxItems: 1
54
55 phy-names:
56 items:
57 - const: csis
58
59 power-domains:
60 maxItems: 1
61
62 vddio-supply:
63 description: MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V).
64
65 vddcore-supply:
66 description: MIPI CSIS Core voltage supply (e.g. 1.1V).
67
68 patternProperties:
69 "^port@[34]$":
70 $ref: /schemas/graph.yaml#/$defs/port-base
71 additionalProperties: false
72 description:
73 Camera input port.
74
75 properties:
76 reg:
77 enum: [3, 4]
78
79 endpoint:
80 $ref: video-interfaces.yaml#
81 unevaluatedProperties: false
82
83 properties:
84 data-lanes:
85 minItems: 1
86 maxItems: 4
87
88 samsung,csis-hs-settle:
89 $ref: /schemas/types.yaml#/definitions/uint32
90 description: Differential receiver (HS-RX) settle time.
91
92 samsung,csis-wclk:
93 type: boolean
94 description:
95 CSI-2 wrapper clock selection. If this property is present external clock
96 from CMU will be used, or the bus clock if it's not specified.
97
98 required:
99 - data-lanes
100
101 required:
102 - reg
103
104 required:
105 - compatible
106 - reg
107 - bus-width
108 - clocks
109 - clock-names
110 - interrupts
111 - vddio-supply
112 - vddcore-supply
113
114 anyOf:
115 - required:
116 - port@3
117 - required:
118 - port@4
119
120 allOf:
121 - if:
122 required:
123 - samsung,isp-wb
124 then:
125 required:
126 - samsung,sysreg
127
128 additionalProperties: false
129
130 examples:
131 - |
132 #include <dt-bindings/clock/exynos4.h>
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
134
135 csis@11890000 {
136 compatible = "samsung,exynos4210-csis";
137 reg = <0x11890000 0x4000>;
138 clocks = <&clock CLK_CSIS1>,
139 <&clock CLK_SCLK_CSIS1>;
140 clock-names = "csis", "sclk_csis";
141 assigned-clocks = <&clock CLK_MOUT_CSIS1>,
142 <&clock CLK_SCLK_CSIS1>;
143 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
144 assigned-clock-rates = <0>, <176000000>;
145
146 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
147
148 bus-width = <2>;
149 power-domains = <&pd_cam>;
150 phys = <&mipi_phy 2>;
151 phy-names = "csis";
152
153 vddcore-supply = <&ldo8_reg>;
154 vddio-supply = <&ldo10_reg>;
155
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 /* Camera D (4) MIPI CSI-2 (CSIS1) */
160 port@4 {
161 reg = <4>;
162
163 endpoint {
164 remote-endpoint = <&is_s5k6a3_ep>;
165 data-lanes = <1>;
166 samsung,csis-hs-settle = <18>;
167 samsung,csis-wclk;
168 };
169 };
170 };
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