1 Xilinx Video Test Pattern Generator (TPG)
2 -----------------------------------------
3
4 Required properties:
5
6 - compatible: Must contain at least one of
7
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
10
11 TPG versions backward-compatible with previous versions should list all
12 compatible versions in the newer to older order.
13
14 - reg: Physical base address and length of the registers set for the device.
15
16 - clocks: Reference to the video core clock.
17
18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
19 video.txt.
20
21 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
22 The TPG has a single output port numbered 0.
23
24 Optional properties:
25
26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
27 video timings for the TPG test patterns.
28
29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
30 input. The GPIO active level corresponds to the selection of VTC-generated
31 video timings.
32
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
34 synthesized with two ports and forbidden when synthesized with one port.
35
36 Example:
37
38 tpg_0: tpg@40050000 {
39 compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
40 reg = <0x40050000 0x10000>;
41 clocks = <&clkc 15>;
42
43 xlnx,vtc = <&vtc_3>;
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
45
46 ports {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 port@0 {
51 reg = <0>;
52
53 xlnx,video-format = <XVIP_VF_YUV_422>;
54 xlnx,video-width = <8>;
55
56 tpg_in: endpoint {
57 remote-endpoint = <&adv7611_out>;
58 };
59 };
60 port@1 {
61 reg = <1>;
62
63 xlnx,video-format = <XVIP_VF_YUV_422>;
64 xlnx,video-width = <8>;
65
66 tpg1_out: endpoint {
67 remote-endpoint = <&switch_in0>;
68 };
69 };
70 };
71 };
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