1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Samsung Exynos SoC SROM Controller driver
8
9 maintainers:
10 - Krzysztof Kozlowski <krzk@kernel.org>
11
12 description: |+
13 The SROM controller can be used to attach external peripherals. In this case
14 extra properties, describing the bus behind it, should be specified.
15
16 properties:
17 compatible:
18 items:
19 - const: samsung,exynos4210-srom
20
21 reg:
22 maxItems: 1
23
24 "#address-cells":
25 const: 2
26
27 "#size-cells":
28 const: 1
29
30 ranges:
31 minItems: 1
32 maxItems: 4
33 description: |
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
36 Up to four banks are supported.
37
38 patternProperties:
39 "^.*@[0-3],[a-f0-9]+$":
40 type: object
41 additionalProperties: true
42 description:
43 The actual device nodes should be added as subnodes to the SROMc node.
44 These subnodes, in addition to regular device specification, should
45 contain the following properties, describing configuration
46 of the relevant SROM bank.
47
48 properties:
49 reg:
50 description:
51 Bank number, base address (relative to start of the bank) and size
52 of the memory mapped for the device. Note that base address will be
53 typically 0 as this is the start of the bank.
54 maxItems: 1
55
56 reg-io-width:
57 enum: [1, 2]
58 description:
59 Data width in bytes (1 or 2). If omitted, default of 1 is used.
60
61 samsung,srom-page-mode:
62 description:
63 If page mode is set, 4 data page mode will be configured,
64 else normal (1 data) page mode will be set.
65 type: boolean
66
67 samsung,srom-timing:
68 $ref: /schemas/types.yaml#/definitions/uint32-array
69 items:
70 minItems: 6
71 maxItems: 6
72 description: |
73 Array of 6 integers, specifying bank timings in the following order:
74 Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
75 Each value is specified in cycles and has the following meaning
76 and valid range:
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
83
84 required:
85 - reg
86 - samsung,srom-timing
87
88 required:
89 - compatible
90 - reg
91
92 additionalProperties: false
93
94 examples:
95 - |
96 // Example: basic definition, no banks are configured
97 memory-controller@12560000 {
98 compatible = "samsung,exynos4210-srom";
99 reg = <0x12560000 0x14>;
100 };
101
102 - |
103 // Example: SROMc with SMSC911x ethernet chip on bank 3
104 memory-controller@12570000 {
105 #address-cells = <2>;
106 #size-cells = <1>;
107 ranges = <0 0 0x04000000 0x20000 // Bank0
108 1 0 0x05000000 0x20000 // Bank1
109 2 0 0x06000000 0x20000 // Bank2
110 3 0 0x07000000 0x20000>; // Bank3
111
112 compatible = "samsung,exynos4210-srom";
113 reg = <0x12570000 0x14>;
114
115 ethernet@3,0 {
116 compatible = "smsc,lan9115";
117 reg = <3 0 0x10000>; // Bank 3, offset = 0
118 phy-mode = "mii";
119 interrupt-parent = <&gpx0>;
120 interrupts = <5 8>;
121 reg-io-width = <2>;
122 smsc,irq-push-pull;
123 smsc,force-internal-phy;
124
125 samsung,srom-page-mode;
126 samsung,srom-timing = <9 12 1 9 1 1>;
127 };
128 };
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