1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Intel IXP4xx Expansion Bus Controller
8
9 description: |
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
12 including IXP42x, IXP43x, IXP45x and IXP46x.
13
14 maintainers:
15 - Linus Walleij <linus.walleij@linaro.org>
16
17 properties:
18 $nodename:
19 pattern: '^bus@[0-9a-f]+$'
20
21 compatible:
22 items:
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
25 - intel,ixp43x-expansion-bus-controller
26 - intel,ixp45x-expansion-bus-controller
27 - intel,ixp46x-expansion-bus-controller
28 - const: syscon
29
30 reg:
31 description: Control registers for the expansion bus, these are not
32 inside the memory range handled by the expansion bus.
33 maxItems: 1
34
35 native-endian:
36 $ref: /schemas/types.yaml#/definitions/flag
37 description: The IXP4xx has a peculiar MMIO access scheme, as it changes
38 the access pattern for words (swizzling) on the bus depending on whether
39 the SoC is running in big-endian or little-endian mode. Thus the
40 registers must always be accessed using native endianness.
41
42 "#address-cells":
43 description: |
44 The first cell is the chip select number.
45 The second cell is the address offset within the bank.
46 const: 2
47
48 "#size-cells":
49 const: 1
50
51 ranges: true
52 dma-ranges: true
53
54 patternProperties:
55 "^.*@[0-7],[0-9a-f]+$":
56 description: Devices attached to chip selects are represented as
57 subnodes.
58 type: object
59 $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
60 additionalProperties: true
61
62 required:
63 - compatible
64 - reg
65 - native-endian
66 - "#address-cells"
67 - "#size-cells"
68 - ranges
69 - dma-ranges
70
71 additionalProperties: false
72
73 examples:
74 - |
75 #include <dt-bindings/interrupt-controller/irq.h>
76 bus@50000000 {
77 compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
78 reg = <0xc4000000 0x28>;
79 native-endian;
80 #address-cells = <2>;
81 #size-cells = <1>;
82 ranges = <0 0x0 0x50000000 0x01000000>,
83 <1 0x0 0x51000000 0x01000000>;
84 dma-ranges = <0 0x0 0x50000000 0x01000000>,
85 <1 0x0 0x51000000 0x01000000>;
86 flash@0,0 {
87 compatible = "intel,ixp4xx-flash", "cfi-flash";
88 bank-width = <2>;
89 reg = <0 0x00000000 0x1000000>;
90 intel,ixp4xx-eb-t3 = <3>;
91 intel,ixp4xx-eb-cycle-type = <0>;
92 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
93 intel,ixp4xx-eb-write-enable = <1>;
94 intel,ixp4xx-eb-byte-access = <0>;
95 };
96 serial@1,0 {
97 compatible = "exar,xr16l2551", "ns8250";
98 reg = <1 0x00000000 0x10>;
99 interrupt-parent = <&gpio0>;
100 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
101 clock-frequency = <1843200>;
102 intel,ixp4xx-eb-t3 = <3>;
103 intel,ixp4xx-eb-cycle-type = <1>;
104 intel,ixp4xx-eb-write-enable = <1>;
105 intel,ixp4xx-eb-byte-access = <1>;
106 };
107 };
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