1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
8
9 maintainers:
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
12
13 description: |
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
18
19 Up to 15 GiB of physical memory can be supported. Security features such as
20 encryption of traffic to and from DRAM via general security apertures are
21 available for video and other secure applications, as well as DRAM ECC for
22 automotive safety applications (single bit error correction and double bit
23 error detection).
24
25 properties:
26 $nodename:
27 pattern: "^memory-controller@[0-9a-f]+$"
28
29 compatible:
30 items:
31 - enum:
32 - nvidia,tegra186-mc
33 - nvidia,tegra194-mc
34 - nvidia,tegra234-mc
35
36 reg:
37 minItems: 6
38 maxItems: 18
39
40 reg-names:
41 minItems: 6
42 maxItems: 18
43
44 interrupts:
45 items:
46 - description: MC general interrupt
47
48 "#address-cells":
49 const: 2
50
51 "#size-cells":
52 const: 2
53
54 ranges: true
55
56 dma-ranges: true
57
58 "#interconnect-cells":
59 const: 1
60
61 patternProperties:
62 "^external-memory-controller@[0-9a-f]+$":
63 description:
64 The bulk of the work involved in controlling the external memory
65 controller on NVIDIA Tegra186 and later is performed on the BPMP. This
66 coprocessor exposes the EMC clock that is used to set the frequency at
67 which the external memory is clocked and a remote procedure call that
68 can be used to obtain the set of available frequencies.
69 type: object
70 properties:
71 compatible:
72 items:
73 - enum:
74 - nvidia,tegra186-emc
75 - nvidia,tegra194-emc
76 - nvidia,tegra234-emc
77
78 reg:
79 minItems: 1
80 maxItems: 2
81
82 interrupts:
83 items:
84 - description: EMC general interrupt
85
86 clocks:
87 items:
88 - description: external memory clock
89
90 clock-names:
91 items:
92 - const: emc
93
94 "#interconnect-cells":
95 const: 0
96
97 nvidia,bpmp:
98 $ref: /schemas/types.yaml#/definitions/phandle
99 description:
100 phandle of the node representing the BPMP
101
102 allOf:
103 - if:
104 properties:
105 compatible:
106 const: nvidia,tegra186-emc
107 then:
108 properties:
109 reg:
110 maxItems: 1
111
112 - if:
113 properties:
114 compatible:
115 const: nvidia,tegra194-emc
116 then:
117 properties:
118 reg:
119 minItems: 2
120
121 - if:
122 properties:
123 compatible:
124 const: nvidia,tegra234-emc
125 then:
126 properties:
127 reg:
128 minItems: 2
129
130 additionalProperties: false
131
132 required:
133 - compatible
134 - reg
135 - interrupts
136 - clocks
137 - clock-names
138 - "#interconnect-cells"
139 - nvidia,bpmp
140
141 allOf:
142 - if:
143 properties:
144 compatible:
145 const: nvidia,tegra186-mc
146 then:
147 properties:
148 reg:
149 maxItems: 6
150 description: 5 memory controller channels and 1 for stream-id registers
151
152 reg-names:
153 items:
154 - const: sid
155 - const: broadcast
156 - const: ch0
157 - const: ch1
158 - const: ch2
159 - const: ch3
160
161 - if:
162 properties:
163 compatible:
164 const: nvidia,tegra194-mc
165 then:
166 properties:
167 reg:
168 minItems: 18
169 description: 17 memory controller channels and 1 for stream-id registers
170
171 reg-names:
172 items:
173 - const: sid
174 - const: broadcast
175 - const: ch0
176 - const: ch1
177 - const: ch2
178 - const: ch3
179 - const: ch4
180 - const: ch5
181 - const: ch6
182 - const: ch7
183 - const: ch8
184 - const: ch9
185 - const: ch10
186 - const: ch11
187 - const: ch12
188 - const: ch13
189 - const: ch14
190 - const: ch15
191
192 - if:
193 properties:
194 compatible:
195 const: nvidia,tegra234-mc
196 then:
197 properties:
198 reg:
199 minItems: 18
200 description: 17 memory controller channels and 1 for stream-id registers
201
202 reg-names:
203 items:
204 - const: sid
205 - const: broadcast
206 - const: ch0
207 - const: ch1
208 - const: ch2
209 - const: ch3
210 - const: ch4
211 - const: ch5
212 - const: ch6
213 - const: ch7
214 - const: ch8
215 - const: ch9
216 - const: ch10
217 - const: ch11
218 - const: ch12
219 - const: ch13
220 - const: ch14
221 - const: ch15
222
223 additionalProperties: false
224
225 required:
226 - compatible
227 - reg
228 - reg-names
229 - interrupts
230 - "#address-cells"
231 - "#size-cells"
232
233 examples:
234 - |
235 #include <dt-bindings/clock/tegra186-clock.h>
236 #include <dt-bindings/interrupt-controller/arm-gic.h>
237
238 bus {
239 #address-cells = <2>;
240 #size-cells = <2>;
241
242 memory-controller@2c00000 {
243 compatible = "nvidia,tegra186-mc";
244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
250 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
251 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
252
253 #address-cells = <2>;
254 #size-cells = <2>;
255
256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
257
258 /*
259 * Memory clients have access to all 40 bits that the memory
260 * controller can address.
261 */
262 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
263
264 external-memory-controller@2c60000 {
265 compatible = "nvidia,tegra186-emc";
266 reg = <0x0 0x02c60000 0x0 0x50000>;
267 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&bpmp TEGRA186_CLK_EMC>;
269 clock-names = "emc";
270
271 #interconnect-cells = <0>;
272
273 nvidia,bpmp = <&bpmp>;
274 };
275 };
276 };
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