1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
8
9 description: |
10 The FMC2 functional block makes the interface with: synchronous and
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
12 peripherals) and NAND flash memories.
13 Its main purposes are:
14 - to translate AXI transactions into the appropriate external device
15 protocol
16 - to meet the access time requirements of the external devices
17 All external devices share the addresses, data and control signals with the
18 controller. Each external device is accessed by means of a unique Chip
19 Select. The FMC2 performs only one access at a time to an external device.
20
21 maintainers:
22 - Christophe Kerello <christophe.kerello@foss.st.com>
23
24 properties:
25 compatible:
26 enum:
27 - st,stm32mp1-fmc2-ebi
28 - st,stm32mp25-fmc2-ebi
29
30 reg:
31 maxItems: 1
32
33 clocks:
34 maxItems: 1
35
36 resets:
37 maxItems: 1
38
39 power-domains:
40 maxItems: 1
41
42 "#address-cells":
43 const: 2
44
45 "#size-cells":
46 const: 1
47
48 ranges:
49 description: |
50 Reflects the memory layout with four integer values per bank. Format:
51 <bank-number> 0 <address of the bank> <size>
52
53 access-controllers:
54 minItems: 1
55 maxItems: 2
56
57 patternProperties:
58 "^.*@[0-4],[a-f0-9]+$":
59 additionalProperties: true
60 type: object
61 $ref: mc-peripheral-props.yaml#
62
63 required:
64 - "#address-cells"
65 - "#size-cells"
66 - compatible
67 - reg
68 - clocks
69 - ranges
70
71 additionalProperties: false
72
73 examples:
74 - |
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 #include <dt-bindings/clock/stm32mp1-clks.h>
77 #include <dt-bindings/reset/stm32mp1-resets.h>
78 memory-controller@58002000 {
79 #address-cells = <2>;
80 #size-cells = <1>;
81 compatible = "st,stm32mp1-fmc2-ebi";
82 reg = <0x58002000 0x1000>;
83 clocks = <&rcc FMC_K>;
84 resets = <&rcc FMC_R>;
85
86 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
87 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
88 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
89 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
90 <4 0 0x80000000 0x10000000>; /* NAND */
91
92 psram@0,0 {
93 compatible = "mtd-ram";
94 reg = <0 0x00000000 0x100000>;
95 bank-width = <2>;
96
97 st,fmc2-ebi-cs-transaction-type = <1>;
98 st,fmc2-ebi-cs-address-setup-ns = <60>;
99 st,fmc2-ebi-cs-data-setup-ns = <30>;
100 st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
101 };
102
103 nand-controller@4,0 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 compatible = "st,stm32mp1-fmc2-nfc";
107 reg = <4 0x00000000 0x1000>,
108 <4 0x08010000 0x1000>,
109 <4 0x08020000 0x1000>,
110 <4 0x01000000 0x1000>,
111 <4 0x09010000 0x1000>,
112 <4 0x09020000 0x1000>;
113 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
114 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
115 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
116 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
117 dma-names = "tx", "rx", "ecc";
118
119 nand@0 {
120 reg = <0>;
121 nand-on-flash-bbt;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 };
125 };
126 };
127
128 ...
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