1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # # Copyright (c) 2021 Aspeed Tehchnology Inc.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Aspeed Low Pin Count (LPC) Bus Controller
9
10 maintainers:
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
13
14 description:
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
16 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
17 primary use case of the Aspeed LPC controller is as a slave on the bus
18 (typically in a Baseboard Management Controller SoC), but under certain
19 conditions it can also take the role of bus master.
20
21 The LPC controller is represented as a multi-function device to account for the
22 mix of functionality, which includes, but is not limited to
23
24 * An IPMI Block Transfer[2] Controller
25
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
28 management and bus snoop configuration.
29
30 * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom
31 hardware management protocols for handover between the host and baseboard
32 management controller.
33
34 Additionally the state of the LPC controller influences the pinmux
35 configuration, therefore the host portion of the controller is exposed as a
36 syscon as a means to arbitrate access.
37
38 properties:
39 compatible:
40 items:
41 - enum:
42 - aspeed,ast2400-lpc-v2
43 - aspeed,ast2500-lpc-v2
44 - aspeed,ast2600-lpc-v2
45 - const: simple-mfd
46 - const: syscon
47
48 reg:
49 maxItems: 1
50
51 "#address-cells":
52 const: 1
53
54 "#size-cells":
55 const: 1
56
57 ranges: true
58
59 patternProperties:
60 "^lpc-ctrl@[0-9a-f]+$":
61 type: object
62 additionalProperties: false
63
64 description: |
65 The LPC Host Interface Controller manages functions exposed to the host such as
66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
67 and bus snoop configuration.
68
69 properties:
70 compatible:
71 items:
72 - enum:
73 - aspeed,ast2400-lpc-ctrl
74 - aspeed,ast2500-lpc-ctrl
75 - aspeed,ast2600-lpc-ctrl
76
77 reg:
78 maxItems: 1
79
80 clocks:
81 maxItems: 1
82
83 memory-region:
84 maxItems: 1
85 description: handle to memory reservation for the LPC to AHB mapping region
86
87 flash:
88 $ref: /schemas/types.yaml#/definitions/phandle
89 description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
90
91 required:
92 - compatible
93 - clocks
94
95 "^reset-controller@[0-9a-f]+$":
96 type: object
97 additionalProperties: false
98
99 description:
100 The UARTs present in the ASPEED SoC can have their resets tied to the reset
101 state of the LPC bus. Some systems may chose to modify this configuration
102
103 properties:
104 compatible:
105 items:
106 - enum:
107 - aspeed,ast2400-lpc-reset
108 - aspeed,ast2500-lpc-reset
109 - aspeed,ast2600-lpc-reset
110
111 reg:
112 maxItems: 1
113
114 '#reset-cells':
115 const: 1
116
117 required:
118 - compatible
119 - '#reset-cells'
120
121 "^lpc-snoop@[0-9a-f]+$":
122 type: object
123 additionalProperties: false
124
125 description:
126 The LPC snoop interface allows the BMC to listen on and record the data
127 bytes written by the Host to the targeted LPC I/O pots.
128
129 properties:
130 compatible:
131 items:
132 - enum:
133 - aspeed,ast2400-lpc-snoop
134 - aspeed,ast2500-lpc-snoop
135 - aspeed,ast2600-lpc-snoop
136
137 reg:
138 maxItems: 1
139
140 interrupts:
141 maxItems: 1
142
143 snoop-ports:
144 $ref: /schemas/types.yaml#/definitions/uint32-array
145 description: The LPC I/O ports to snoop
146
147 required:
148 - compatible
149 - interrupts
150 - snoop-ports
151
152 "^uart-routing@[0-9a-f]+$":
153 $ref: /schemas/soc/aspeed/uart-routing.yaml#
154 description: The UART routing control under LPC register space
155
156 required:
157 - compatible
158 - reg
159 - "#address-cells"
160 - "#size-cells"
161 - ranges
162
163 additionalProperties:
164 type: object
165
166 examples:
167 - |
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #include <dt-bindings/clock/ast2600-clock.h>
170
171 lpc: lpc@1e789000 {
172 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
173 reg = <0x1e789000 0x1000>;
174
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges = <0x0 0x1e789000 0x1000>;
178
179 lpc_ctrl: lpc-ctrl@80 {
180 compatible = "aspeed,ast2600-lpc-ctrl";
181 reg = <0x80 0x80>;
182 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
183 memory-region = <&flash_memory>;
184 flash = <&spi>;
185 };
186
187 lpc_reset: reset-controller@98 {
188 compatible = "aspeed,ast2600-lpc-reset";
189 reg = <0x98 0x4>;
190 #reset-cells = <1>;
191 };
192
193 lpc_snoop: lpc-snoop@90 {
194 compatible = "aspeed,ast2600-lpc-snoop";
195 reg = <0x90 0x8>;
196 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
197 snoop-ports = <0x80>;
198 };
199 };
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