1 * Broadcom cable/DSL/settop platforms
2
3 Required properties:
4
5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
7 "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
8 "brcm,bcm63168", "brcm,bcm63268",
9 "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
10 "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
11
12 The experimental -viper variants are for running Linux on the 3384's
13 BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
14
15 Power management
16 ----------------
17
18 For power management (particularly, S2/S3/S5 system suspend), the following SoC
19 components are needed:
20
21 = Always-On control block (AON CTRL)
22
23 This hardware provides control registers for the "always-on" (even in low-power
24 modes) hardware, such as the Power Management State Machine (PMSM).
25
26 Required properties:
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
31 "brcm,brcmstb-aon-ctrl"
32 - reg : the register start and length for the AON CTRL block
33
34 Example:
35
36 syscon@410000 {
37 compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
38 reg = <0x410000 0x400>;
39 };
40
41 = Memory controllers
42
43 A Broadcom STB SoC typically has a number of independent memory controllers,
44 each of which may have several associated hardware blocks, which are versioned
45 independently (control registers, DDR PHYs, etc.). One might consider
46 describing these controllers as a parent "memory controllers" block, which
47 contains N sub-nodes (one for each controller in the system), each of which is
48 associated with a number of hardware register resources (e.g., its PHY.
49
50 == MEMC (MEMory Controller)
51
52 Represents a single memory controller instance.
53
54 Required properties:
55 - compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
56 - ranges : should contain the child address in the parent address
57 space, must be 0 here, and the register start and length of
58 the entire memory controller (including all sub nodes: DDR PHY,
59 arbiter, etc.)
60 - #address-cells : must be 1
61 - #size-cells : must be 1
62
63 Example:
64
65 memory-controller@0 {
66 compatible = "brcm,brcmstb-memc", "simple-bus";
67 ranges = <0x0 0x0 0xa000>;
68 #address-cells = <1>;
69 #size-cells = <1>;
70
71 memc-arb@1000 {
72 ...
73 };
74
75 memc-ddr@2000 {
76 ...
77 };
78
79 ddr-phy@6000 {
80 ...
81 };
82 };
83
84 Should contain subnodes for any of the following relevant hardware resources:
85
86 == DDR PHY control
87
88 Control registers for this memory controller's DDR PHY.
89
90 Required properties:
91 - compatible : should contain one of these
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
94
95 - reg : the DDR PHY register range and length
96
97 Example:
98
99 ddr-phy@6000 {
100 compatible = "brcm,brcmstb-ddr-phy-v64.5";
101 reg = <0x6000 0xc8>;
102 };
103
104 == DDR memory controller sequencer
105
106 Control registers for this memory controller's DDR memory sequencer
107
108 Required properties:
109 - compatible : should contain one of these
110 "brcm,bcm7425-memc-ddr"
111 "brcm,bcm7429-memc-ddr"
112 "brcm,bcm7435-memc-ddr" and
113 "brcm,brcmstb-memc-ddr"
114
115 - reg : the DDR sequencer register range and length
116
117 Example:
118
119 memc-ddr@2000 {
120 compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
121 reg = <0x2000 0x300>;
122 };
123
124 == MEMC Arbiter
125
126 The memory controller arbiter is responsible for memory clients allocation
127 (bandwidth, priorities etc.) and needs to have its contents restored during
128 deep sleep states (S3).
129
130 Required properties:
131
132 - compatible : should contain one of these
133 "brcm,brcmstb-memc-arb-v10.0.0.0"
134 "brcm,brcmstb-memc-arb"
135
136 - reg : the DDR Arbiter register range and length
137
138 Example:
139
140 memc-arb@1000 {
141 compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
142 reg = <0x1000 0x248>;
143 };
144
145 == Timers
146
147 The Broadcom STB chips contain a timer block with several general purpose
148 timers that can be used.
149
150 Required properties:
151
152 - compatible : should contain one of:
153 "brcm,bcm7425-timers"
154 "brcm,bcm7429-timers"
155 "brcm,bcm7435-timers" and
156 "brcm,brcmstb-timers"
157 - reg : the timers register range
158 - interrupts : the interrupt line for this timer block
159
160 Example:
161
162 timers: timer@4067c0 {
163 compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
164 reg = <0x4067c0 0x40>;
165 interrupts = <&periph_intc 19>;
166 };
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