1 * UCTL SATA controller glue
2
3 UCTL is the bridge unit between the I/O interconnect (an internal bus)
4 and the SATA AHCI host controller (UAHC). It performs the following functions:
5 - provides interfaces for the applications to access the UAHC AHCI
6 registers on the CN71XX I/O space.
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
8 buffers from Level 2 Cache.
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
14
15 Properties:
16
17 - compatible: "cavium,octeon-7130-sata-uctl"
18
19 Compatibility with the cn7130 SOC.
20
21 - reg: The base address of the UCTL register bank.
22
23 - #address-cells, #size-cells, ranges and dma-ranges must be present and hold
24 suitable values to map all child nodes.
25
26 Example:
27
28 uctl@118006c000000 {
29 compatible = "cavium,octeon-7130-sata-uctl";
30 reg = <0x11800 0x6c000000 0x0 0x100>;
31 ranges; /* Direct mapping */
32 dma-ranges;
33 #address-cells = <2>;
34 #size-cells = <2>;
35
36 sata: sata@16c0000000000 {
37 compatible = "cavium,octeon-7130-ahci";
38 reg = <0x16c00 0x00000000 0x0 0x200>;
39 interrupt-parent = <&cibsata>;
40 interrupts = <2 4>; /* Bit: 2, level */
41 };
42 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.