1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Amlogic Meson SDHC controller
8
9 allOf:
10 - $ref: mmc-controller.yaml
11
12 maintainers:
13 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14
15 description: |
16 The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
17 card interface with 1/4/8-bit bus width.
18 It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
19
20 properties:
21 compatible:
22 items:
23 - enum:
24 - amlogic,meson8-sdhc
25 - amlogic,meson8b-sdhc
26 - amlogic,meson8m2-sdhc
27 - const: amlogic,meson-mx-sdhc
28
29 reg:
30 minItems: 1
31
32 interrupts:
33 minItems: 1
34
35 clocks:
36 minItems: 5
37
38 clock-names:
39 items:
40 - const: clkin0
41 - const: clkin1
42 - const: clkin2
43 - const: clkin3
44 - const: pclk
45
46 required:
47 - compatible
48 - reg
49 - interrupts
50 - clocks
51 - clock-names
52
53 unevaluatedProperties: false
54
55 examples:
56 - |
57 #include <dt-bindings/interrupt-controller/irq.h>
58 #include <dt-bindings/interrupt-controller/arm-gic.h>
59
60 sdhc: mmc@8e00 {
61 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
62 reg = <0x8e00 0x42>;
63 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
64 clocks = <&xtal>,
65 <&fclk_div4>,
66 <&fclk_div3>,
67 <&fclk_div5>,
68 <&sdhc_pclk>;
69 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
70 };
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