1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Atmel SDHCI controller
8
9 maintainers:
10 - Aubin Constans <aubin.constans@microchip.com>
11 - Nicolas Ferre <nicolas.ferre@microchip.com>
12
13 description:
14 Bindings for the SDHCI controller found in Atmel/Microchip SoCs.
15
16 properties:
17 compatible:
18 oneOf:
19 - enum:
20 - atmel,sama5d2-sdhci
21 - microchip,sam9x60-sdhci
22 - items:
23 - enum:
24 - microchip,sam9x7-sdhci
25 - microchip,sama7g5-sdhci
26 - const: microchip,sam9x60-sdhci
27
28 reg:
29 maxItems: 1
30
31 interrupts:
32 maxItems: 1
33
34 clocks:
35 items:
36 - description: hclock
37 - description: multclk
38 - description: baseclk
39 minItems: 2
40
41 clock-names:
42 items:
43 - const: hclock
44 - const: multclk
45 - const: baseclk
46 minItems: 2
47
48 microchip,sdcal-inverted:
49 type: boolean
50 description:
51 When present, polarity on the SDCAL SoC pin is inverted. The default
52 polarity for this signal is described in the datasheet. For instance on
53 SAMA5D2, the pin is usually tied to the GND with a resistor and a
54 capacitor (see "SDMMC I/O Calibration" chapter).
55
56 required:
57 - compatible
58 - reg
59 - interrupts
60 - clocks
61 - clock-names
62
63 allOf:
64 - $ref: sdhci-common.yaml#
65 - if:
66 properties:
67 compatible:
68 contains:
69 enum:
70 - atmel,sama5d2-sdhci
71 then:
72 properties:
73 clocks:
74 minItems: 3
75 clock-names:
76 minItems: 3
77
78 unevaluatedProperties: false
79
80 examples:
81 - |
82 #include <dt-bindings/interrupt-controller/irq.h>
83 #include <dt-bindings/clock/at91.h>
84 mmc@a0000000 {
85 compatible = "atmel,sama5d2-sdhci";
86 reg = <0xa0000000 0x300>;
87 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
88 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
89 clock-names = "hclock", "multclk", "baseclk";
90 assigned-clocks = <&sdmmc0_gclk>;
91 assigned-clock-rates = <480000000>;
92 };
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