1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Nuvoton MA35D1 SD/SDIO/MMC Controller
8
9 maintainers:
10 - Shan-Chun Hung <shanchun1218@gmail.com>
11
12 allOf:
13 - $ref: sdhci-common.yaml#
14
15 properties:
16 compatible:
17 enum:
18 - nuvoton,ma35d1-sdhci
19
20 reg:
21 maxItems: 1
22
23 interrupts:
24 maxItems: 1
25
26 clocks:
27 maxItems: 1
28
29 pinctrl-names:
30 minItems: 1
31 items:
32 - const: default
33 - const: state_uhs
34
35 pinctrl-0:
36 description:
37 Should contain default/high speed pin ctrl.
38 maxItems: 1
39
40 pinctrl-1:
41 description:
42 Should contain uhs mode pin ctrl.
43 maxItems: 1
44
45 resets:
46 maxItems: 1
47
48 nuvoton,sys:
49 $ref: /schemas/types.yaml#/definitions/phandle
50 description: phandle to access GCR (Global Control Register) registers.
51
52 required:
53 - compatible
54 - reg
55 - interrupts
56 - clocks
57 - pinctrl-names
58 - pinctrl-0
59 - resets
60 - nuvoton,sys
61
62 unevaluatedProperties: false
63
64 examples:
65 - |
66 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
68 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
69
70 soc {
71 #address-cells = <2>;
72 #size-cells = <2>;
73 mmc@40190000 {
74 compatible = "nuvoton,ma35d1-sdhci";
75 reg = <0x0 0x40190000 0x0 0x2000>;
76 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk SDH1_GATE>;
78 pinctrl-names = "default", "state_uhs";
79 pinctrl-0 = <&pinctrl_sdhci1>;
80 pinctrl-1 = <&pinctrl_sdhci1_uhs>;
81 resets = <&sys MA35D1_RESET_SDH1>;
82 nuvoton,sys = <&sys>;
83 vqmmc-supply = <&sdhci1_vqmmc_regulator>;
84 bus-width = <8>;
85 max-frequency = <200000000>;
86 };
87 };
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