1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SDHCI controller (sdhci-msm)
8
9 maintainers:
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12 description:
13 Secure Digital Host Controller Interface (SDHCI) present on
14 Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16 properties:
17 compatible:
18 oneOf:
19 - enum:
20 - qcom,sdhci-msm-v4
21 deprecated: true
22 - items:
23 - enum:
24 - qcom,apq8084-sdhci
25 - qcom,ipq4019-sdhci
26 - qcom,ipq8074-sdhci
27 - qcom,msm8226-sdhci
28 - qcom,msm8953-sdhci
29 - qcom,msm8974-sdhci
30 - qcom,msm8976-sdhci
31 - qcom,msm8916-sdhci
32 - qcom,msm8992-sdhci
33 - qcom,msm8994-sdhci
34 - qcom,msm8996-sdhci
35 - qcom,msm8998-sdhci
36 - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
37 - items:
38 - enum:
39 - qcom,ipq5018-sdhci
40 - qcom,ipq5332-sdhci
41 - qcom,ipq6018-sdhci
42 - qcom,ipq9574-sdhci
43 - qcom,qcm2290-sdhci
44 - qcom,qcs404-sdhci
45 - qcom,qdu1000-sdhci
46 - qcom,sc7180-sdhci
47 - qcom,sc7280-sdhci
48 - qcom,sc8280xp-sdhci
49 - qcom,sdm630-sdhci
50 - qcom,sdm670-sdhci
51 - qcom,sdm845-sdhci
52 - qcom,sdx55-sdhci
53 - qcom,sdx65-sdhci
54 - qcom,sdx75-sdhci
55 - qcom,sm6115-sdhci
56 - qcom,sm6125-sdhci
57 - qcom,sm6350-sdhci
58 - qcom,sm6375-sdhci
59 - qcom,sm8150-sdhci
60 - qcom,sm8250-sdhci
61 - qcom,sm8350-sdhci
62 - qcom,sm8450-sdhci
63 - qcom,sm8550-sdhci
64 - qcom,sm8650-sdhci
65 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
66
67 reg:
68 minItems: 1
69 maxItems: 4
70
71 reg-names:
72 minItems: 1
73 maxItems: 4
74
75 clocks:
76 minItems: 2
77 items:
78 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
79 - description: SDC MMC clock, MCLK
80 - description: TCXO clock
81 - description: clock for Inline Crypto Engine
82 - description: SDCC bus voter clock
83 - description: reference clock for RCLK delay calibration
84 - description: sleep clock for RCLK delay calibration
85
86 clock-names:
87 minItems: 2
88 items:
89 - const: iface
90 - const: core
91 - const: xo
92 - enum: [ice, bus, cal, sleep]
93 - enum: [ice, bus, cal, sleep]
94 - enum: [ice, bus, cal, sleep]
95 - enum: [ice, bus, cal, sleep]
96
97 dma-coherent: true
98
99 interrupts:
100 maxItems: 2
101
102 interrupt-names:
103 items:
104 - const: hc_irq
105 - const: pwr_irq
106
107 pinctrl-names:
108 minItems: 1
109 items:
110 - const: default
111 - const: sleep
112
113 pinctrl-0:
114 description:
115 Should specify pin control groups used for this controller.
116
117 pinctrl-1:
118 description:
119 Should specify sleep pin control groups used for this controller.
120
121 resets:
122 maxItems: 1
123
124 qcom,ddr-config:
125 $ref: /schemas/types.yaml#/definitions/uint32
126 description: platform specific settings for DDR_CONFIG reg.
127
128 qcom,dll-config:
129 $ref: /schemas/types.yaml#/definitions/uint32
130 description: platform specific settings for DLL_CONFIG reg.
131
132 iommus:
133 minItems: 1
134 maxItems: 8
135 description: |
136 phandle to apps_smmu node with sid mask.
137
138 interconnects:
139 minItems: 1
140 items:
141 - description: data path, sdhc to ddr
142 - description: config path, cpu to sdhc
143
144 interconnect-names:
145 minItems: 1
146 items:
147 - const: sdhc-ddr
148 - const: cpu-sdhc
149
150 power-domains:
151 description: A phandle to sdhci power domain node
152 maxItems: 1
153
154 operating-points-v2: true
155
156 patternProperties:
157 '^opp-table(-[a-z0-9]+)?$':
158 if:
159 properties:
160 compatible:
161 const: operating-points-v2
162 then:
163 patternProperties:
164 '^opp-?[0-9]+$':
165 required:
166 - required-opps
167
168 required:
169 - compatible
170 - reg
171 - clocks
172 - clock-names
173 - interrupts
174
175 allOf:
176 - $ref: sdhci-common.yaml#
177
178 - if:
179 properties:
180 compatible:
181 contains:
182 enum:
183 - qcom,sdhci-msm-v4
184 then:
185 properties:
186 reg:
187 minItems: 2
188 items:
189 - description: Host controller register map
190 - description: SD Core register map
191 - description: CQE register map
192 - description: Inline Crypto Engine register map
193 reg-names:
194 minItems: 2
195 items:
196 - const: hc
197 - const: core
198 - const: cqhci
199 - const: ice
200 else:
201 properties:
202 reg:
203 minItems: 1
204 items:
205 - description: Host controller register map
206 - description: CQE register map
207 - description: Inline Crypto Engine register map
208 reg-names:
209 minItems: 1
210 items:
211 - const: hc
212 - const: cqhci
213 - const: ice
214
215 unevaluatedProperties: false
216
217 examples:
218 - |
219 #include <dt-bindings/interrupt-controller/arm-gic.h>
220 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
221 #include <dt-bindings/clock/qcom,rpmh.h>
222 #include <dt-bindings/power/qcom,rpmhpd.h>
223
224 sdhc_2: mmc@8804000 {
225 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
226 reg = <0 0x08804000 0 0x1000>;
227
228 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "hc_irq", "pwr_irq";
231
232 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
233 <&gcc GCC_SDCC2_APPS_CLK>,
234 <&rpmhcc RPMH_CXO_CLK>;
235 clock-names = "iface", "core", "xo";
236 iommus = <&apps_smmu 0x4a0 0x0>;
237 qcom,dll-config = <0x0007642c>;
238 qcom,ddr-config = <0x80040868>;
239 power-domains = <&rpmhpd RPMHPD_CX>;
240
241 operating-points-v2 = <&sdhc2_opp_table>;
242
243 sdhc2_opp_table: opp-table {
244 compatible = "operating-points-v2";
245
246 opp-19200000 {
247 opp-hz = /bits/ 64 <19200000>;
248 required-opps = <&rpmhpd_opp_min_svs>;
249 };
250
251 opp-50000000 {
252 opp-hz = /bits/ 64 <50000000>;
253 required-opps = <&rpmhpd_opp_low_svs>;
254 };
255
256 opp-100000000 {
257 opp-hz = /bits/ 64 <100000000>;
258 required-opps = <&rpmhpd_opp_svs>;
259 };
260
261 opp-202000000 {
262 opp-hz = /bits/ 64 <202000000>;
263 required-opps = <&rpmhpd_opp_svs_l1>;
264 };
265 };
266 };
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