1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Synopsys Designware Mobile Storage Host Controller
8
9 maintainers:
10 - Ulf Hansson <ulf.hansson@linaro.org>
11
12 # Everything else is described in the common file
13 properties:
14 compatible:
15 enum:
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
19
20 reg:
21 maxItems: 1
22
23 interrupts:
24 maxItems: 1
25
26 clocks:
27 minItems: 2
28 maxItems: 2
29 description:
30 Handle to "biu" and "ciu" clocks for the
31 bus interface unit clock and the card interface unit clock.
32
33 clock-names:
34 items:
35 - const: biu
36 - const: ciu
37
38 iommus:
39 maxItems: 1
40
41 altr,sysmgr-syscon:
42 $ref: /schemas/types.yaml#/definitions/phandle-array
43 items:
44 - items:
45 - description: phandle to the sysmgr node
46 - description: register offset that controls the SDMMC clock phase
47 - description: register shift for the smplsel(drive in) setting
48 description:
49 This property is optional. Contains the phandle to System Manager block
50 that contains the SDMMC clock-phase control register. The first value is
51 the pointer to the sysmgr, the 2nd value is the register offset for the
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
53 smplsel(drive in) setting.
54
55 allOf:
56 - $ref: synopsys-dw-mshc-common.yaml#
57
58 - if:
59 properties:
60 compatible:
61 contains:
62 const: altr,socfpga-dw-mshc
63 then:
64 properties:
65 altr,sysmgr-syscon: true
66 else:
67 properties:
68 iommus: false
69 altr,sysmgr-syscon: false
70
71 required:
72 - compatible
73 - reg
74 - interrupts
75 - clocks
76 - clock-names
77
78 unevaluatedProperties: false
79
80 examples:
81 - |
82 mmc@12200000 {
83 compatible = "snps,dw-mshc";
84 reg = <0x12200000 0x1000>;
85 interrupts = <0 75 0>;
86 clocks = <&clock 351>, <&clock 132>;
87 clock-names = "biu", "ciu";
88 dmas = <&pdma 12>;
89 dma-names = "rx-tx";
90 resets = <&rst 20>;
91 reset-names = "reset";
92 vmmc-supply = <&buck8>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95 broken-cd;
96 bus-width = <8>;
97 cap-mmc-highspeed;
98 cap-sd-highspeed;
99 card-detect-delay = <200>;
100 max-frequency = <200000000>;
101 clock-frequency = <400000000>;
102 data-addr = <0x200>;
103 fifo-depth = <0x80>;
104 fifo-watermark-aligned;
105 };
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