1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
8
9 maintainers:
10 - Rob Herring <robh@kernel.org>
11
12 allOf:
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
15
16 properties:
17 compatible:
18 oneOf:
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
21 (m25p(40|80|16|32|64|128)|\
22 n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
23 atmel,at25df(321a|641|081a)|\
24 everspin,mr25h(10|40|128|256)|\
25 (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
26 (mxicy|macronix),mx25u(4033|4035)|\
27 (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
28 (sst|microchip),sst25vf(016b|032b|040b)|\
29 (sst,)?sst26wf016b|\
30 (sst,)?sst25wf(040b|080)|\
31 winbond,w25x(80|32)|\
32 (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
33 - const: jedec,spi-nor
34 - items:
35 - enum:
36 - issi,is25lp016d
37 - micron,mt25qu02g
38 - mxicy,mx25r1635f
39 - mxicy,mx25u6435f
40 - mxicy,mx25v8035f
41 - spansion,s25sl12801
42 - spansion,s25fs512s
43 - const: jedec,spi-nor
44 - const: jedec,spi-nor
45 description:
46 SPI NOR flashes compatible with the JEDEC SFDP standard or which may be
47 identified with the READ ID opcode (0x9F) do not deserve a specific
48 compatible. They should instead only be matched against the generic
49 "jedec,spi-nor" compatible.
50
51 reg:
52 minItems: 1
53 maxItems: 2
54
55 interrupts:
56 maxItems: 1
57
58 m25p,fast-read:
59 type: boolean
60 description:
61 Use the "fast read" opcode to read data from the chip instead of the usual
62 "read" opcode. This opcode is not supported by all chips and support for
63 it can not be detected at runtime. Refer to your chips' datasheet to check
64 if this is supported by your chip.
65
66 broken-flash-reset:
67 type: boolean
68 description:
69 Some flash devices utilize stateful addressing modes (e.g., for 32-bit
70 addressing) which need to be managed carefully by a system. Because these
71 sorts of flash don't have a standardized software reset command, and
72 because some systems don't toggle the flash RESET# pin upon system reset
73 (if the pin even exists at all), there are systems which cannot reboot
74 properly if the flash is left in the "wrong" state. This boolean flag can
75 be used on such systems, to denote the absence of a reliable reset
76 mechanism.
77
78 no-wp:
79 type: boolean
80 description:
81 The status register write disable (SRWD) bit in status register, combined
82 with the WP# signal, provides hardware data protection for the device. When
83 the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
84 strapped to LOW, the status register nonvolatile bits become read-only and
85 the WRITE STATUS REGISTER operation will not execute. The only way to exit
86 this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the
87 flash device is not connected or is wrongly tied to GND (that includes internal
88 pull-downs) then status register permanently becomes read-only as the SRWD bit
89 cannot be reset. This boolean flag can be used on such systems to avoid setting
90 the SRWD bit while writing the status register. WP# signal hard strapped to GND
91 can be a valid use case.
92
93 reset-gpios:
94 description:
95 A GPIO line connected to the RESET (active low) signal of the device.
96 If "broken-flash-reset" is present then having this property does not
97 make any difference.
98
99 spi-cpol: true
100 spi-cpha: true
101
102 dependencies:
103 spi-cpol: [ spi-cpha ]
104 spi-cpha: [ spi-cpol ]
105
106 unevaluatedProperties: false
107
108 examples:
109 - |
110 #include <dt-bindings/gpio/gpio.h>
111 spi {
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 flash@0 {
116 compatible = "spansion,m25p80", "jedec,spi-nor";
117 reg = <0>;
118 spi-max-frequency = <40000000>;
119 m25p,fast-read;
120 reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
121 };
122 };
123 ...
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