1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek(MTK) SoCs NAND ECC engine
8
9 maintainers:
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
11
12 description: |
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
14
15 properties:
16 compatible:
17 enum:
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
21 - mediatek,mt7986-ecc
22
23 reg:
24 items:
25 - description: Base physical address and size of ECC.
26
27 interrupts:
28 items:
29 - description: ECC interrupt
30
31 clocks:
32 maxItems: 1
33
34 clock-names:
35 const: nfiecc_clk
36
37 required:
38 - compatible
39 - reg
40 - interrupts
41 - clocks
42 - clock-names
43
44 additionalProperties: false
45
46 examples:
47 - |
48 #include <dt-bindings/clock/mt2701-clk.h>
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51
52 soc {
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 bch: ecc@1100e000 {
57 compatible = "mediatek,mt2701-ecc";
58 reg = <0 0x1100e000 0 0x1000>;
59 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
60 clocks = <&pericfg CLK_PERI_NFI_ECC>;
61 clock-names = "nfiecc_clk";
62 };
63 };
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