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Linux/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Qualcomm NAND controller
  8 
  9 maintainers:
 10   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 11 
 12 properties:
 13   compatible:
 14     enum:
 15       - qcom,ipq806x-nand
 16       - qcom,ipq4019-nand
 17       - qcom,ipq6018-nand
 18       - qcom,ipq8074-nand
 19       - qcom,sdx55-nand
 20 
 21   reg:
 22     maxItems: 1
 23 
 24   clocks:
 25     items:
 26       - description: Core Clock
 27       - description: Always ON Clock
 28 
 29   clock-names:
 30     items:
 31       - const: core
 32       - const: aon
 33 
 34   qcom,cmd-crci:
 35     $ref: /schemas/types.yaml#/definitions/uint32
 36     description:
 37       Must contain the ADM command type CRCI block instance number specified for
 38       the NAND controller on the given platform
 39 
 40   qcom,data-crci:
 41     $ref: /schemas/types.yaml#/definitions/uint32
 42     description:
 43       Must contain the ADM data type CRCI block instance number specified for
 44       the NAND controller on the given platform
 45 
 46 patternProperties:
 47   "^nand@[a-f0-9]$":
 48     type: object
 49     $ref: raw-nand-chip.yaml
 50     properties:
 51 
 52       nand-bus-width:
 53         const: 8
 54 
 55       nand-ecc-strength:
 56         enum: [1, 4, 8]
 57 
 58       nand-ecc-step-size:
 59         enum:
 60           - 512
 61 
 62       qcom,boot-partitions:
 63         $ref: /schemas/types.yaml#/definitions/uint32-matrix
 64         items:
 65           items:
 66             - description: offset
 67             - description: size
 68         description:
 69           Boot partition use a different layout where the 4 bytes of spare
 70           data are not protected by ECC. Use this to declare these special
 71           partitions by defining first the offset and then the size.
 72 
 73           It's in the form of <offset1 size1 offset2 size2 offset3 ...>
 74           and should be declared in ascending order.
 75 
 76           Refer to the ipq8064 example on how to use this special binding.
 77 
 78     unevaluatedProperties: false
 79 
 80 allOf:
 81   - $ref: nand-controller.yaml#
 82 
 83   - if:
 84       properties:
 85         compatible:
 86           contains:
 87             const: qcom,ipq806x-nand
 88     then:
 89       properties:
 90         dmas:
 91           items:
 92             - description: rxtx DMA channel
 93 
 94         dma-names:
 95           items:
 96             - const: rxtx
 97 
 98   - if:
 99       properties:
100         compatible:
101           contains:
102             enum:
103               - qcom,ipq4019-nand
104               - qcom,ipq6018-nand
105               - qcom,ipq8074-nand
106               - qcom,sdx55-nand
107 
108     then:
109       properties:
110         dmas:
111           items:
112             - description: tx DMA channel
113             - description: rx DMA channel
114             - description: cmd DMA channel
115 
116         dma-names:
117           items:
118             - const: tx
119             - const: rx
120             - const: cmd
121 
122         qcom,cmd-crci: false
123         qcom,data-crci: false
124 
125       patternProperties:
126         "^nand@[a-f0-9]$":
127           properties:
128             qcom,boot-partitions: false
129 
130 required:
131   - compatible
132   - reg
133   - clocks
134   - clock-names
135 
136 unevaluatedProperties: false
137 
138 examples:
139   - |
140     #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
141     nand-controller@1ac00000 {
142         compatible = "qcom,ipq806x-nand";
143         reg = <0x1ac00000 0x800>;
144 
145         clocks = <&gcc EBI2_CLK>,
146                  <&gcc EBI2_AON_CLK>;
147         clock-names = "core", "aon";
148 
149         dmas = <&adm_dma 3>;
150         dma-names = "rxtx";
151         qcom,cmd-crci = <15>;
152         qcom,data-crci = <3>;
153 
154         #address-cells = <1>;
155         #size-cells = <0>;
156 
157         nand@0 {
158             reg = <0>;
159 
160             nand-ecc-strength = <4>;
161             nand-bus-width = <8>;
162 
163             qcom,boot-partitions = <0x0 0x58a0000>;
164 
165             partitions {
166                 compatible = "fixed-partitions";
167                 #address-cells = <1>;
168                 #size-cells = <1>;
169 
170                 partition@0 {
171                     label = "boot-nand";
172                     reg = <0 0x58a0000>;
173                 };
174 
175                 partition@58a0000 {
176                     label = "fs-nand";
177                     reg = <0x58a0000 0x4000000>;
178                 };
179             };
180         };
181     };
182 
183     #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
184     nand-controller@79b0000 {
185         compatible = "qcom,ipq4019-nand";
186         reg = <0x79b0000 0x1000>;
187 
188         clocks = <&gcc GCC_QPIC_CLK>,
189                  <&gcc GCC_QPIC_AHB_CLK>;
190         clock-names = "core", "aon";
191 
192         dmas = <&qpicbam 0>,
193                <&qpicbam 1>,
194                <&qpicbam 2>;
195         dma-names = "tx", "rx", "cmd";
196 
197         #address-cells = <1>;
198         #size-cells = <0>;
199 
200         nand@0 {
201             reg = <0>;
202             nand-ecc-strength = <4>;
203             nand-bus-width = <8>;
204 
205             partitions {
206                 compatible = "fixed-partitions";
207                 #address-cells = <1>;
208                 #size-cells = <1>;
209 
210                 partition@0 {
211                     label = "boot-nand";
212                     reg = <0 0x58a0000>;
213                 };
214 
215                 partition@58a0000 {
216                     label = "fs-nand";
217                     reg = <0x58a0000 0x4000000>;
218                 };
219             };
220         };
221     };
222 
223 ...

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