1 APM X-Gene SoC Ethernet nodes
2
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
5
6 Required properties for all the ethernet interfaces:
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
14 - "enet_csr": Ethernet control and status register address space
15 - "ring_csr": Descriptor ring control and status register address space
16 - "ring_cmd": Descriptor ring command register address space
17 - interrupts: Two interrupt specifiers can be specified.
18 - First is the Rx interrupt. This irq is mandatory.
19 - Second is the Tx completion interrupt.
20 This is supported only on SGMII based 1GbE and 10GbE interfaces.
21 - channel: Ethernet to CPU, start channel (prefetch buffer) number
22 - Must map to the first irq and irqs must be sequential
23 - port-id: Port number (0 or 1)
24 - clocks: Reference to the clock entry.
25 - local-mac-address: MAC address assigned to this device
26 - phy-connection-type: Interface type between ethernet device and PHY device
27
28 Required properties for ethernet interfaces that have external PHY:
29 - phy-handle: Reference to a PHY node connected to this device
30
31 - mdio: Device tree subnode with the following required properties:
32 - compatible: Must be "apm,xgene-mdio".
33 - #address-cells: Must be <1>.
34 - #size-cells: Must be <0>.
35
36 For the phy on the mdio bus, there must be a node with the following fields:
37 - compatible: PHY identifier. Please refer ./phy.txt for the format.
38 - reg: The ID number for the phy.
39
40 Optional properties:
41 - status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
42 - tx-delay: Delay value for RGMII bridge TX clock.
43 Valid values are between 0 to 7, that maps to
44 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
45 Default value is 4, which corresponds to 1611 ps
46 - rx-delay: Delay value for RGMII bridge RX clock.
47 Valid values are between 0 to 7, that maps to
48 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
49 Default value is 2, which corresponds to 899 ps
50 - rxlos-gpios: Input gpio from SFP+ module to indicate availability of
51 incoming signal.
52
53
54 Example:
55 menetclk: menetclk {
56 compatible = "apm,xgene-device-clock";
57 clock-output-names = "menetclk";
58 status = "ok";
59 };
60
61 menet: ethernet@17020000 {
62 compatible = "apm,xgene-enet";
63 status = "disabled";
64 reg = <0x0 0x17020000 0x0 0xd100>,
65 <0x0 0x17030000 0x0 0x400>,
66 <0x0 0x10000000 0x0 0x200>;
67 reg-names = "enet_csr", "ring_csr", "ring_cmd";
68 interrupts = <0x0 0x3c 0x4>;
69 port-id = <0>;
70 clocks = <&menetclk 0>;
71 local-mac-address = [00 01 73 00 00 01];
72 phy-connection-type = "rgmii";
73 phy-handle = <&menetphy>;
74 mdio {
75 compatible = "apm,xgene-mdio";
76 #address-cells = <1>;
77 #size-cells = <0>;
78 menetphy: menetphy@3 {
79 compatible = "ethernet-phy-id001c.c915";
80 reg = <0x3>;
81 };
82
83 };
84 };
85
86 /* Board-specific peripheral configurations */
87 &menet {
88 tx-delay = <4>;
89 rx-delay = <2>;
90 status = "ok";
91 };
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