1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas R-Car CAN Controller
8
9 maintainers:
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
11
12 properties:
13 compatible:
14 oneOf:
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
19 - const: renesas,rcar-gen1-can # R-Car Gen1
20
21 - items:
22 - enum:
23 - renesas,can-r8a7742 # RZ/G1H
24 - renesas,can-r8a7743 # RZ/G1M
25 - renesas,can-r8a7744 # RZ/G1N
26 - renesas,can-r8a7745 # RZ/G1E
27 - renesas,can-r8a77470 # RZ/G1C
28 - renesas,can-r8a7790 # R-Car H2
29 - renesas,can-r8a7791 # R-Car M2-W
30 - renesas,can-r8a7792 # R-Car V2H
31 - renesas,can-r8a7793 # R-Car M2-N
32 - renesas,can-r8a7794 # R-Car E2
33 - const: renesas,rcar-gen2-can # R-Car Gen2 and RZ/G1
34
35 - items:
36 - enum:
37 - renesas,can-r8a774a1 # RZ/G2M
38 - renesas,can-r8a774b1 # RZ/G2N
39 - renesas,can-r8a774c0 # RZ/G2E
40 - renesas,can-r8a774e1 # RZ/G2H
41 - renesas,can-r8a7795 # R-Car H3
42 - renesas,can-r8a7796 # R-Car M3-W
43 - renesas,can-r8a77961 # R-Car M3-W+
44 - renesas,can-r8a77965 # R-Car M3-N
45 - renesas,can-r8a77990 # R-Car E3
46 - renesas,can-r8a77995 # R-Car D3
47 - const: renesas,rcar-gen3-can # R-Car Gen3 and RZ/G2
48
49 reg:
50 maxItems: 1
51
52 interrupts:
53 maxItems: 1
54
55 clocks:
56 maxItems: 3
57
58 clock-names:
59 items:
60 - const: clkp1
61 - const: clkp2
62 - const: can_clk
63
64 power-domains:
65 maxItems: 1
66
67 resets:
68 maxItems: 1
69
70 renesas,can-clock-select:
71 $ref: /schemas/types.yaml#/definitions/uint32
72 enum: [ 0, 1, 3 ]
73 default: 0
74 description: |
75 R-Car CAN Clock Source Select. Valid values are:
76 <0x0> (default) : Peripheral clock (clkp1)
77 <0x1> : Peripheral clock (clkp2)
78 <0x3> : External input clock
79
80 assigned-clocks:
81 description:
82 Reference to the clkp2 (CANFD) clock.
83 On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock. This is a div6
84 clock and can be used by both CAN and CAN FD controllers at the same
85 time. It needs to be scaled to maximum frequency if any of these
86 controllers use it.
87
88 assigned-clock-rates:
89 description: Maximum frequency of the CANFD clock.
90
91 required:
92 - compatible
93 - reg
94 - interrupts
95 - clocks
96 - clock-names
97 - power-domains
98
99 allOf:
100 - $ref: can-controller.yaml#
101
102 - if:
103 not:
104 properties:
105 compatible:
106 contains:
107 const: renesas,rcar-gen1-can
108 then:
109 required:
110 - resets
111
112 - if:
113 properties:
114 compatible:
115 contains:
116 const: renesas,rcar-gen3-can
117 then:
118 required:
119 - assigned-clocks
120 - assigned-clock-rates
121
122 unevaluatedProperties: false
123
124 examples:
125 - |
126 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
127 #include <dt-bindings/interrupt-controller/arm-gic.h>
128 #include <dt-bindings/power/r8a7791-sysc.h>
129
130 can0: can@e6e80000 {
131 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
132 reg = <0xe6e80000 0x1000>;
133 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&cpg CPG_MOD 916>,
135 <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
136 clock-names = "clkp1", "clkp2", "can_clk";
137 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
138 resets = <&cpg 916>;
139 };
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