1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/cdns,macb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Cadence MACB/GEM Ethernet controller
8
9 maintainers:
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
12
13 properties:
14 compatible:
15 oneOf:
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
20
21 - items:
22 - enum:
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
26 deprecated: true
27
28 - items:
29 - enum:
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
34
35 - items:
36 - enum:
37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38 - cdns,sam9x60-macb # Microchip sam9x60 SoC
39 - microchip,mpfs-macb # Microchip PolarFire SoC
40 - const: cdns,macb # Generic
41
42 - items:
43 - enum:
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
45 - enum:
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47 - const: cdns,macb # Generic
48
49 - enum:
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
54 - cdns,np4-macb # NP4 SoC devices
55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
58 - cdns,emac # Generic
59 - cdns,gem # Generic
60 - cdns,macb # Generic
61
62 - items:
63 - enum:
64 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface
65 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
66
67 reg:
68 minItems: 1
69 items:
70 - description: Basic register set
71 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
72
73 interrupts:
74 minItems: 1
75 maxItems: 8
76 description: One interrupt per available hardware queue
77
78 clocks:
79 minItems: 1
80 maxItems: 5
81
82 clock-names:
83 minItems: 1
84 items:
85 - enum: [ ether_clk, hclk, pclk ]
86 - enum: [ hclk, pclk ]
87 - const: tx_clk
88 - enum: [ rx_clk, tsu_clk ]
89 - const: tsu_clk
90
91 local-mac-address: true
92
93 phy-mode: true
94
95 phy-handle: true
96
97 phys:
98 maxItems: 1
99
100 resets:
101 maxItems: 1
102 description:
103 Recommended with ZynqMP, specify reset control for this
104 controller instance with zynqmp-reset driver.
105
106 reset-names:
107 maxItems: 1
108
109 fixed-link: true
110
111 iommus:
112 maxItems: 1
113
114 power-domains:
115 maxItems: 1
116
117 cdns,rx-watermark:
118 $ref: /schemas/types.yaml#/definitions/uint32
119 description:
120 When the receive partial store and forward mode is activated,
121 the receiver will only begin to forward the packet to the external
122 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
123 rx-watermark corresponds to the number of SRAM buffer locations,
124 that need to be filled, before the forwarding process is activated.
125 Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
126
127 '#address-cells':
128 const: 1
129
130 '#size-cells':
131 const: 0
132
133 mdio:
134 type: object
135 description:
136 Node containing PHY children. If this node is not present, then PHYs will
137 be direct children.
138
139 patternProperties:
140 "^ethernet-phy@[0-9a-f]$":
141 type: object
142 $ref: ethernet-phy.yaml#
143
144 properties:
145 reset-gpios: true
146
147 magic-packet:
148 type: boolean
149 deprecated: true
150 description:
151 Indicates that the hardware supports waking up via magic packet.
152
153 unevaluatedProperties: false
154
155 required:
156 - compatible
157 - reg
158 - interrupts
159 - clocks
160 - clock-names
161 - phy-mode
162
163 allOf:
164 - $ref: ethernet-controller.yaml#
165
166 - if:
167 not:
168 properties:
169 compatible:
170 contains:
171 const: sifive,fu540-c000-gem
172 then:
173 properties:
174 reg:
175 maxItems: 1
176
177 unevaluatedProperties: false
178
179 examples:
180 - |
181 macb0: ethernet@fffc4000 {
182 compatible = "cdns,macb";
183 reg = <0xfffc4000 0x4000>;
184 interrupts = <21>;
185 cdns,rx-watermark = <0x44>;
186 phy-mode = "rmii";
187 local-mac-address = [3a 0e 03 04 05 06];
188 clock-names = "pclk", "hclk", "tx_clk";
189 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
190 #address-cells = <1>;
191 #size-cells = <0>;
192
193 ethernet-phy@1 {
194 reg = <0x1>;
195 reset-gpios = <&pioE 6 1>;
196 };
197 };
198
199 - |
200 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
201 #include <dt-bindings/power/xlnx-zynqmp-power.h>
202 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
203 #include <dt-bindings/phy/phy.h>
204
205 bus {
206 #address-cells = <2>;
207 #size-cells = <2>;
208 gem1: ethernet@ff0c0000 {
209 compatible = "xlnx,zynqmp-gem", "cdns,gem";
210 interrupt-parent = <&gic>;
211 interrupts = <0 59 4>, <0 59 4>;
212 reg = <0x0 0xff0c0000 0x0 0x1000>;
213 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
214 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
215 <&zynqmp_clk GEM_TSU>;
216 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 iommus = <&smmu 0x875>;
220 power-domains = <&zynqmp_firmware PD_ETH_1>;
221 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
222 reset-names = "gem1_rst";
223 phy-mode = "sgmii";
224 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
225 fixed-link {
226 speed = <1000>;
227 full-duplex;
228 pause;
229 };
230 };
231 };
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