1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Realtek switches for unmanaged switches
8
9 allOf:
10 - $ref: dsa.yaml#/$defs/ethernet-ports
11
12 maintainers:
13 - Linus Walleij <linus.walleij@linaro.org>
14
15 description:
16 Realtek advertises these chips as fast/gigabit switches or unmanaged
17 switches. They can be controlled using different interfaces, like SMI,
18 MDIO or SPI.
19
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
22 not use the MDIO protocol. This binding defines how to specify the
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
24 and it must be inserted inside a platform node.
25
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
28 an MDIO node.
29
30 The compatible string is only used to identify which (silicon) family the
31 switch belongs to. Roughly speaking, a family is any set of Realtek switches
32 whose chip identification register(s) have a common location and semantics.
33 The different models in a given family can be automatically disambiguated by
34 parsing the chip identification register(s) according to the given family,
35 avoiding the need for a unique compatible string for each model.
36
37 properties:
38 compatible:
39 enum:
40 - realtek,rtl8365mb
41 - realtek,rtl8366rb
42 description: |
43 realtek,rtl8365mb:
44 Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
45 RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
46 RTL8367SB, RTL8370MB, RTL8310SR
47 realtek,rtl8366rb:
48 Use with models RTL8366RB, RTL8366S
49
50 mdc-gpios:
51 description: GPIO line for the MDC clock line.
52 maxItems: 1
53
54 mdio-gpios:
55 description: GPIO line for the MDIO data line.
56 maxItems: 1
57
58 reset-gpios:
59 description: GPIO to be used to reset the whole device
60 maxItems: 1
61
62 resets:
63 maxItems: 1
64
65 realtek,disable-leds:
66 type: boolean
67 description: |
68 if the LED drivers are not used in the hardware design,
69 this will disable them so they are not turned on
70 and wasting power.
71
72 interrupt-controller:
73 type: object
74 additionalProperties: false
75
76 description: |
77 This defines an interrupt controller with an IRQ line (typically
78 a GPIO) that will demultiplex and handle the interrupt from the single
79 interrupt line coming out of one of the Realtek switch chips. It most
80 importantly provides link up/down interrupts to the PHY blocks inside
81 the ASIC.
82
83 properties:
84
85 interrupt-controller: true
86
87 interrupts:
88 maxItems: 1
89 description:
90 A single IRQ line from the switch, either active LOW or HIGH
91
92 '#address-cells':
93 const: 0
94
95 '#interrupt-cells':
96 const: 1
97
98 required:
99 - interrupt-controller
100 - '#address-cells'
101 - '#interrupt-cells'
102
103 mdio:
104 $ref: /schemas/net/mdio.yaml#
105 unevaluatedProperties: false
106
107 properties:
108 compatible:
109 const: realtek,smi-mdio
110
111 if:
112 required:
113 - reg
114
115 then:
116 $ref: /schemas/spi/spi-peripheral-props.yaml#
117 not:
118 required:
119 - mdc-gpios
120 - mdio-gpios
121 - mdio
122
123 properties:
124 mdc-gpios: false
125 mdio-gpios: false
126 mdio: false
127
128 else:
129 required:
130 - mdc-gpios
131 - mdio-gpios
132 - mdio
133
134 required:
135 - compatible
136
137 # - mdc-gpios
138 # - mdio-gpios
139 # - reset-gpios
140 # - mdio
141
142 unevaluatedProperties: false
143
144 examples:
145 - |
146 #include <dt-bindings/gpio/gpio.h>
147 #include <dt-bindings/interrupt-controller/irq.h>
148
149 platform {
150 switch {
151 compatible = "realtek,rtl8366rb";
152 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
153 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
154 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
155 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
156
157 switch_intc1: interrupt-controller {
158 /* GPIO 15 provides the interrupt */
159 interrupt-parent = <&gpio0>;
160 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <1>;
164 };
165
166 ports {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 port@0 {
170 reg = <0>;
171 label = "lan0";
172 phy-handle = <&phy0>;
173 };
174 port@1 {
175 reg = <1>;
176 label = "lan1";
177 phy-handle = <&phy1>;
178 };
179 port@2 {
180 reg = <2>;
181 label = "lan2";
182 phy-handle = <&phy2>;
183 };
184 port@3 {
185 reg = <3>;
186 label = "lan3";
187 phy-handle = <&phy3>;
188 };
189 port@4 {
190 reg = <4>;
191 label = "wan";
192 phy-handle = <&phy4>;
193 };
194 port@5 {
195 reg = <5>;
196 ethernet = <&gmac0>;
197 phy-mode = "rgmii";
198 fixed-link {
199 speed = <1000>;
200 full-duplex;
201 };
202 };
203 };
204
205 mdio {
206 compatible = "realtek,smi-mdio";
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 phy0: ethernet-phy@0 {
211 reg = <0>;
212 interrupt-parent = <&switch_intc1>;
213 interrupts = <0>;
214 };
215 phy1: ethernet-phy@1 {
216 reg = <1>;
217 interrupt-parent = <&switch_intc1>;
218 interrupts = <1>;
219 };
220 phy2: ethernet-phy@2 {
221 reg = <2>;
222 interrupt-parent = <&switch_intc1>;
223 interrupts = <2>;
224 };
225 phy3: ethernet-phy@3 {
226 reg = <3>;
227 interrupt-parent = <&switch_intc1>;
228 interrupts = <3>;
229 };
230 phy4: ethernet-phy@4 {
231 reg = <4>;
232 interrupt-parent = <&switch_intc1>;
233 interrupts = <12>;
234 };
235 };
236 };
237 };
238
239 - |
240 #include <dt-bindings/gpio/gpio.h>
241 #include <dt-bindings/interrupt-controller/irq.h>
242
243 platform {
244 switch {
245 compatible = "realtek,rtl8365mb";
246 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
247 mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
248 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
249
250 switch_intc2: interrupt-controller {
251 interrupt-parent = <&gpio5>;
252 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
253 interrupt-controller;
254 #address-cells = <0>;
255 #interrupt-cells = <1>;
256 };
257
258 ports {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 port@0 {
262 reg = <0>;
263 label = "swp0";
264 phy-handle = <ðphy0>;
265 };
266 port@1 {
267 reg = <1>;
268 label = "swp1";
269 phy-handle = <ðphy1>;
270 };
271 port@2 {
272 reg = <2>;
273 label = "swp2";
274 phy-handle = <ðphy2>;
275 };
276 port@3 {
277 reg = <3>;
278 label = "swp3";
279 phy-handle = <ðphy3>;
280 };
281 port@6 {
282 reg = <6>;
283 ethernet = <&fec1>;
284 phy-mode = "rgmii";
285 tx-internal-delay-ps = <2000>;
286 rx-internal-delay-ps = <2000>;
287
288 fixed-link {
289 speed = <1000>;
290 full-duplex;
291 pause;
292 };
293 };
294 };
295
296 mdio {
297 compatible = "realtek,smi-mdio";
298 #address-cells = <1>;
299 #size-cells = <0>;
300
301 ethphy0: ethernet-phy@0 {
302 reg = <0>;
303 interrupt-parent = <&switch_intc2>;
304 interrupts = <0>;
305 };
306 ethphy1: ethernet-phy@1 {
307 reg = <1>;
308 interrupt-parent = <&switch_intc2>;
309 interrupts = <1>;
310 };
311 ethphy2: ethernet-phy@2 {
312 reg = <2>;
313 interrupt-parent = <&switch_intc2>;
314 interrupts = <2>;
315 };
316 ethphy3: ethernet-phy@3 {
317 reg = <3>;
318 interrupt-parent = <&switch_intc2>;
319 interrupts = <3>;
320 };
321 };
322 };
323 };
324
325 - |
326 #include <dt-bindings/gpio/gpio.h>
327 #include <dt-bindings/interrupt-controller/irq.h>
328
329 mdio {
330 #address-cells = <1>;
331 #size-cells = <0>;
332
333 switch@29 {
334 compatible = "realtek,rtl8365mb";
335 reg = <29>;
336
337 reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
338
339 switch_intc3: interrupt-controller {
340 interrupt-parent = <&gpio0>;
341 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
342 interrupt-controller;
343 #address-cells = <0>;
344 #interrupt-cells = <1>;
345 };
346
347 ports {
348 #address-cells = <1>;
349 #size-cells = <0>;
350
351 port@0 {
352 reg = <0>;
353 label = "lan4";
354 };
355
356 port@1 {
357 reg = <1>;
358 label = "lan3";
359 };
360
361 port@2 {
362 reg = <2>;
363 label = "lan2";
364 };
365
366 port@3 {
367 reg = <3>;
368 label = "lan1";
369 };
370
371 port@4 {
372 reg = <4>;
373 label = "wan";
374 };
375
376 port@7 {
377 reg = <7>;
378 ethernet = <ðernet>;
379 phy-mode = "rgmii";
380 tx-internal-delay-ps = <2000>;
381 rx-internal-delay-ps = <0>;
382
383 fixed-link {
384 speed = <1000>;
385 full-duplex;
386 };
387 };
388 };
389 };
390 };
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