1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Freescale Frame Manager Device
8
9 maintainers:
10 - Frank Li <Frank.Li@nxp.com>
11
12 description:
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
14 etc.) the FMan node will have child nodes for each of them.
15
16 properties:
17 compatible:
18 enum:
19 - fsl,fman
20 description:
21 FMan version can be determined via FM_IP_REV_1 register in the
22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
24 beginning of the FMan node).
25
26 cell-index:
27 $ref: /schemas/types.yaml#/definitions/uint32
28 description: |
29 Specifies the index of the FMan unit.
30
31 The cell-index value may be used by the SoC, to identify the
32 FMan unit in the SoC memory map. In the table below,
33 there's a description of the cell-index use in each SoC:
34
35 - P1023:
36 register[bit] FMan unit cell-index
37 ============================================================
38 DEVDISR[1] 1 0
39
40 - P2041, P3041, P4080 P5020, P5040:
41 register[bit] FMan unit cell-index
42 ============================================================
43 DCFG_DEVDISR2[6] 1 0
44 DCFG_DEVDISR2[14] 2 1
45 (Second FM available only in P4080 and P5040)
46
47 - B4860, T1040, T2080, T4240:
48 register[bit] FMan unit cell-index
49 ============================================================
50 DCFG_CCSR_DEVDISR2[24] 1 0
51 DCFG_CCSR_DEVDISR2[25] 2 1
52 (Second FM available only in T4240)
53
54 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
55 the specific SoC "Device Configuration/Pin Control" Memory
56 Map.
57
58 reg:
59 items:
60 - description: BMI configuration registers.
61 - description: QMI configuration registers.
62 - description: DMA configuration registers.
63 - description: FPM configuration registers.
64 - description: FMan controller configuration registers.
65 minItems: 1
66
67 ranges: true
68
69 clocks:
70 maxItems: 1
71
72 clock-names:
73 items:
74 - const: fmanclk
75
76 interrupts:
77 items:
78 - description: The first element is associated with the event interrupts.
79 - description: the second element is associated with the error interrupts.
80
81 dma-coherent: true
82
83 ptimer-handle:
84 $ref: /schemas/types.yaml#/definitions/phandle
85 description: see ptp/fsl,ptp.yaml
86
87 fsl,qman-channel-range:
88 $ref: /schemas/types.yaml#/definitions/uint32-array
89 description:
90 Specifies the range of the available dedicated
91 channels in the FMan. The first cell specifies the beginning
92 of the range and the second cell specifies the number of
93 channels
94 items:
95 - description: The first cell specifies the beginning of the range.
96 - description: |
97 The second cell specifies the number of channels.
98 Further information available at:
99 "Work Queue (WQ) Channel Assignments in the QMan" section
100 in DPAA Reference Manual.
101
102 fsl,qman:
103 $ref: /schemas/types.yaml#/definitions/phandle
104 description: See soc/fsl/qman.txt
105
106 fsl,bman:
107 $ref: /schemas/types.yaml#/definitions/phandle
108 description: See soc/fsl/bman.txt
109
110 fsl,erratum-a050385:
111 $ref: /schemas/types.yaml#/definitions/flag
112 description: A boolean property. Indicates the presence of the
113 erratum A050385 which indicates that DMA transactions that are
114 split can result in a FMan lock.
115
116 '#address-cells':
117 const: 1
118
119 '#size-cells':
120 const: 1
121
122 patternProperties:
123 '^muram@[a-f0-9]+$':
124 $ref: fsl,fman-muram.yaml
125
126 '^port@[a-f0-9]+$':
127 $ref: fsl,fman-port.yaml
128
129 '^ethernet@[a-f0-9]+$':
130 $ref: fsl,fman-dtsec.yaml
131
132 '^mdio@[a-f0-9]+$':
133 $ref: fsl,fman-mdio.yaml
134
135 '^phc@[a-f0-9]+$':
136 $ref: /schemas/ptp/fsl,ptp.yaml
137
138 required:
139 - compatible
140 - cell-index
141 - reg
142 - ranges
143 - clocks
144 - clock-names
145 - interrupts
146 - fsl,qman-channel-range
147
148 additionalProperties: false
149
150 examples:
151 - |
152 #include <dt-bindings/interrupt-controller/irq.h>
153
154 fman@400000 {
155 compatible = "fsl,fman";
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x100000>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 cell-index = <1>;
161 clocks = <&fman_clk>;
162 clock-names = "fmanclk";
163 interrupts = <96 IRQ_TYPE_EDGE_FALLING>,
164 <16 IRQ_TYPE_EDGE_FALLING>;
165 fsl,qman-channel-range = <0x40 0xc>;
166
167 muram@0 {
168 compatible = "fsl,fman-muram";
169 reg = <0x0 0x28000>;
170 };
171
172 port@81000 {
173 cell-index = <1>;
174 compatible = "fsl,fman-v2-port-oh";
175 reg = <0x81000 0x1000>;
176 };
177
178 fman1_rx_0x8: port@88000 {
179 cell-index = <0x8>;
180 compatible = "fsl,fman-v2-port-rx";
181 reg = <0x88000 0x1000>;
182 };
183
184 fman1_tx_0x28: port@a8000 {
185 cell-index = <0x28>;
186 compatible = "fsl,fman-v2-port-tx";
187 reg = <0xa8000 0x1000>;
188 };
189
190 ethernet@e0000 {
191 compatible = "fsl,fman-dtsec";
192 cell-index = <0>;
193 reg = <0xe0000 0x1000>;
194 ptp-timer = <&ptp_timer>;
195 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
196 tbi-handle = <&tbi5>;
197 };
198
199 ptp_timer: phc@fe000 {
200 compatible = "fsl,fman-ptp-timer";
201 reg = <0xfe000 0x1000>;
202 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
203 };
204
205 mdio@f1000 {
206 compatible = "fsl,fman-xmdio";
207 reg = <0xf1000 0x1000>;
208 interrupts = <101 IRQ_TYPE_EDGE_FALLING>;
209 };
210 };
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