1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
8
9 maintainers:
10 - Andrew Lunn <andrew@lunn.ch>
11
12 description:
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
14 lines are used to control which child bus is connected.
15
16 allOf:
17 - $ref: /schemas/net/mdio-mux.yaml#
18
19 properties:
20 compatible:
21 const: mdio-mux-gpio
22
23 gpios:
24 description:
25 List of GPIOs used to control the multiplexer, least significant bit first.
26 minItems: 1
27 maxItems: 32
28
29 required:
30 - compatible
31 - gpios
32
33 unevaluatedProperties: false
34
35 examples:
36 - |
37 /*
38 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
39 pair of GPIO lines. Child busses 2 and 3 populated with 4
40 PHYs each.
41 */
42 mdio-mux {
43 compatible = "mdio-mux-gpio";
44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
45 mdio-parent-bus = <&smi1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 mdio@2 {
50 reg = <2>;
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ethernet-phy@1 {
55 reg = <1>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
60 interrupt-parent = <&gpio>;
61 interrupts = <10 8>; /* Pin 10, active low */
62 };
63 ethernet-phy@2 {
64 reg = <2>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
68 <3 0x13 0 0x0a60>;
69 interrupt-parent = <&gpio>;
70 interrupts = <10 8>; /* Pin 10, active low */
71 };
72 ethernet-phy@3 {
73 reg = <3>;
74 marvell,reg-init = <3 0x10 0 0x5777>,
75 <3 0x11 0 0x00aa>,
76 <3 0x12 0 0x4105>,
77 <3 0x13 0 0x0a60>;
78 interrupt-parent = <&gpio>;
79 interrupts = <10 8>; /* Pin 10, active low */
80 };
81 ethernet-phy@4 {
82 reg = <4>;
83 marvell,reg-init = <3 0x10 0 0x5777>,
84 <3 0x11 0 0x00aa>,
85 <3 0x12 0 0x4105>,
86 <3 0x13 0 0x0a60>;
87 interrupt-parent = <&gpio>;
88 interrupts = <10 8>; /* Pin 10, active low */
89 };
90 };
91
92 mdio@3 {
93 reg = <3>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 ethernet-phy@1 {
98 reg = <1>;
99 marvell,reg-init = <3 0x10 0 0x5777>,
100 <3 0x11 0 0x00aa>,
101 <3 0x12 0 0x4105>,
102 <3 0x13 0 0x0a60>;
103 interrupt-parent = <&gpio>;
104 interrupts = <12 8>; /* Pin 12, active low */
105 };
106 ethernet-phy@2 {
107 reg = <2>;
108 marvell,reg-init = <3 0x10 0 0x5777>,
109 <3 0x11 0 0x00aa>,
110 <3 0x12 0 0x4105>,
111 <3 0x13 0 0x0a60>;
112 interrupt-parent = <&gpio>;
113 interrupts = <12 8>; /* Pin 12, active low */
114 };
115 ethernet-phy@3 {
116 reg = <3>;
117 marvell,reg-init = <3 0x10 0 0x5777>,
118 <3 0x11 0 0x00aa>,
119 <3 0x12 0 0x4105>,
120 <3 0x13 0 0x0a60>;
121 interrupt-parent = <&gpio>;
122 interrupts = <12 8>; /* Pin 12, active low */
123 };
124 ethernet-phy@4 {
125 reg = <4>;
126 marvell,reg-init = <3 0x10 0 0x5777>,
127 <3 0x11 0 0x00aa>,
128 <3 0x12 0 0x4105>,
129 <3 0x13 0 0x0a60>;
130 interrupt-parent = <&gpio>;
131 interrupts = <12 8>; /* Pin 12, active low */
132 };
133 };
134 };
135 ...
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