1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
8
9 maintainers:
10 - Andrew Lunn <andrew@lunn.ch>
11
12 description: |+
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
17
18 allOf:
19 - $ref: /schemas/net/mdio-mux.yaml#
20
21 properties:
22 compatible:
23 items:
24 - const: mdio-mux-mmioreg
25 - const: mdio-mux
26
27 reg:
28 description: Contains the offset of the register that controls the bus
29 multiplexer. The size field in the 'reg' property is the size of register,
30 and must therefore be 1, 2, or 4.
31 maxItems: 1
32
33 mux-mask:
34 $ref: /schemas/types.yaml#/definitions/uint32
35 description: Contains an eight-bit mask that specifies which bits in the
36 register control the actual bus multiplexer. The 'reg' property of each
37 child mdio-mux node must be constrained by this mask.
38
39 required:
40 - compatible
41 - reg
42 - mux-mask
43
44 unevaluatedProperties: false
45
46 examples:
47 - |
48 mdio-mux@9 {
49 compatible = "mdio-mux-mmioreg", "mdio-mux";
50 mdio-parent-bus = <&xmdio0>;
51 #address-cells = <1>;
52 #size-cells = <0>;
53 reg = <9 1>; // BRDCFG1
54 mux-mask = <0x6>; // EMI2
55
56 mdio@0 { // Slot 1 XAUI (FM2)
57 reg = <0>;
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 phy_xgmii_slot1: ethernet-phy@4 {
62 compatible = "ethernet-phy-ieee802.3-c45";
63 reg = <4>;
64 };
65 };
66
67 mdio@2 { // Slot 2 XAUI (FM1)
68 reg = <2>;
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 ethernet-phy@4 {
73 compatible = "ethernet-phy-ieee802.3-c45";
74 reg = <4>;
75 };
76 };
77 };
78 ...
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