1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/mscc,miim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Microsemi MII Management Controller (MIIM)
8
9 maintainers:
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11
12 allOf:
13 - $ref: mdio.yaml#
14
15 properties:
16 compatible:
17 enum:
18 - mscc,ocelot-miim
19 - microchip,lan966x-miim
20
21 "#address-cells":
22 const: 1
23
24 "#size-cells":
25 const: 0
26
27 reg:
28 items:
29 - description: base address
30 - description: associated reset register for internal PHYs
31 minItems: 1
32
33 interrupts:
34 maxItems: 1
35
36 clocks:
37 maxItems: 1
38
39 clock-frequency: true
40
41 resets:
42 items:
43 - description:
44 Reset shared with all blocks attached to the Switch Core Register
45 Bus (CSR) including VRAP slave.
46
47 reset-names:
48 items:
49 - const: switch
50
51 required:
52 - compatible
53 - reg
54 - "#address-cells"
55 - "#size-cells"
56
57 unevaluatedProperties: false
58
59 examples:
60 - |
61 mdio@107009c {
62 compatible = "mscc,ocelot-miim";
63 reg = <0x107009c 0x36>, <0x10700f0 0x8>;
64 interrupts = <14>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 phy0: ethernet-phy@0 {
69 reg = <0>;
70 };
71 };
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