1 # SPDX-License-Identifier: GPL-2.0+
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NXP TJA11xx PHY
8
9 maintainers:
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
13
14 description:
15 Bindings for NXP TJA11xx automotive PHYs
16
17 properties:
18 compatible:
19 enum:
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
24 - ethernet-phy-id0180.dd01
25 - ethernet-phy-id0180.dd02
26 - ethernet-phy-id0180.dc80
27 - ethernet-phy-id0180.dc82
28 - ethernet-phy-id001b.b010
29 - ethernet-phy-id001b.b013
30 - ethernet-phy-id001b.b030
31 - ethernet-phy-id001b.b031
32
33 allOf:
34 - $ref: ethernet-phy.yaml#
35 - if:
36 properties:
37 compatible:
38 contains:
39 enum:
40 - ethernet-phy-id0180.dc40
41 - ethernet-phy-id0180.dc41
42 - ethernet-phy-id0180.dc48
43 - ethernet-phy-id0180.dd00
44 - ethernet-phy-id0180.dd01
45 - ethernet-phy-id0180.dd02
46
47 then:
48 properties:
49 nxp,rmii-refclk-in:
50 type: boolean
51 description: |
52 The REF_CLK is provided for both transmitted and received data
53 in RMII mode. This clock signal is provided by the PHY and is
54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
57 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
58 as input or output according to the actual circuit connection.
59 If present, indicates that the REF_CLK will be configured as
60 interface reference clock input when RMII mode enabled.
61 If not present, the REF_CLK will be configured as interface
62 reference clock output when RMII mode enabled.
63 Only supported on TJA1100 and TJA1101.
64
65 patternProperties:
66 "^ethernet-phy@[0-9a-f]+$":
67 type: object
68 additionalProperties: false
69 description: |
70 Some packages have multiple PHYs. Secondary PHY should be defines as
71 subnode of the first (parent) PHY.
72
73 properties:
74 reg:
75 minimum: 0
76 maximum: 31
77 description:
78 The ID number for the child PHY. Should be +1 of parent PHY.
79
80 required:
81 - reg
82
83 unevaluatedProperties: false
84
85 examples:
86 - |
87 mdio {
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 tja1101_phy0: ethernet-phy@4 {
92 compatible = "ethernet-phy-id0180.dc40";
93 reg = <0x4>;
94 nxp,rmii-refclk-in;
95 };
96 };
97 - |
98 mdio {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 tja1102_phy0: ethernet-phy@4 {
103 reg = <0x4>;
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 tja1102_phy1: ethernet-phy@5 {
108 reg = <0x5>;
109 };
110 };
111 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.