1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
8
9 maintainers:
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
12
13 description:
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17 (two external) and provides Ethernet packet communication and switching.
18
19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
21 and one RX channels and operating by NAVSS Unified DMA Peripheral Root
22 Complex (UDMA-P) controller.
23
24 CPSWxG features
25 updated Address Lookup Engine (ALE).
26 priority level Quality Of Service (QOS) support (802.1p)
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
28 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
29 Flow Control (802.3x) Support
30 Time Sensitive Network Support
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
32 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
33 Configurable number of addresses plus VLANs
34 Configurable number of classifier/policers
35 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
37 RX/TX csum offload
38 Management Data Input/Output (MDIO) interface for PHYs management
39 RMII/RGMII Interfaces support
40 new version of Common Platform Time Sync (CPTS)
41
42 The CPSWxG NUSS is integrated into
43 device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
44 device MAIN domain named CPSW0 on AM642x SoC.
45
46 Specifications can be found at
47 https://www.ti.com/lit/pdf/spruid7
48 https://www.ti.com/lit/zip/spruil1
49 https://www.ti.com/lit/pdf/spruim2
50
51 properties:
52 "#address-cells": true
53 "#size-cells": true
54
55 compatible:
56 enum:
57 - ti,am642-cpsw-nuss
58 - ti,am654-cpsw-nuss
59 - ti,j7200-cpswxg-nuss
60 - ti,j721e-cpsw-nuss
61 - ti,j721e-cpswxg-nuss
62 - ti,j784s4-cpswxg-nuss
63
64 reg:
65 maxItems: 1
66 description:
67 The physical base address and size of full the CPSWxG NUSS IO range
68
69 reg-names:
70 items:
71 - const: cpsw_nuss
72
73 ranges: true
74
75 dma-coherent: true
76
77 clocks:
78 maxItems: 1
79 description: CPSWxG NUSS functional clock
80
81 clock-names:
82 items:
83 - const: fck
84
85 assigned-clock-parents: true
86
87 assigned-clocks: true
88
89 power-domains:
90 maxItems: 1
91
92 dmas:
93 maxItems: 9
94
95 dma-names:
96 items:
97 - const: tx0
98 - const: tx1
99 - const: tx2
100 - const: tx3
101 - const: tx4
102 - const: tx5
103 - const: tx6
104 - const: tx7
105 - const: rx
106
107 ethernet-ports:
108 type: object
109 properties:
110 '#address-cells':
111 const: 1
112 '#size-cells':
113 const: 0
114
115 patternProperties:
116 "^port@[1-8]$":
117 type: object
118 description: CPSWxG NUSS external ports
119
120 $ref: ethernet-controller.yaml#
121 unevaluatedProperties: false
122
123 properties:
124 reg:
125 minimum: 1
126 maximum: 8
127 description: CPSW port number
128
129 phys:
130 minItems: 1
131 items:
132 - description: CPSW MAC's PHY.
133 - description: Serdes PHY. Serdes PHY is required only if
134 the Serdes has to be configured in the
135 Single-Link configuration.
136
137 phy-names:
138 minItems: 1
139 items:
140 - const: mac
141 - const: serdes
142
143 label:
144 description: label associated with this port
145
146 ti,mac-only:
147 $ref: /schemas/types.yaml#/definitions/flag
148 description:
149 Specifies the port works in mac-only mode.
150
151 ti,syscon-efuse:
152 $ref: /schemas/types.yaml#/definitions/phandle-array
153 items:
154 - items:
155 - description: Phandle to the system control device node which
156 provides access to efuse
157 - description: offset to efuse registers???
158 description:
159 Phandle to the system control device node which provides access
160 to efuse IO range with MAC addresses
161
162 required:
163 - reg
164 - phys
165
166 additionalProperties: false
167
168 patternProperties:
169 "^mdio@[0-9a-f]+$":
170 type: object
171 $ref: ti,davinci-mdio.yaml#
172
173 description:
174 CPSW MDIO bus.
175
176 "^cpts@[0-9a-f]+":
177 type: object
178 $ref: ti,k3-am654-cpts.yaml#
179 description:
180 CPSW Common Platform Time Sync (CPTS) module.
181
182 required:
183 - compatible
184 - reg
185 - reg-names
186 - ranges
187 - clocks
188 - clock-names
189 - power-domains
190 - dmas
191 - dma-names
192 - '#address-cells'
193 - '#size-cells'
194
195 allOf:
196 - if:
197 not:
198 properties:
199 compatible:
200 contains:
201 enum:
202 - ti,j721e-cpswxg-nuss
203 - ti,j784s4-cpswxg-nuss
204 then:
205 properties:
206 ethernet-ports:
207 patternProperties:
208 "^port@[5-8]$": false
209 "^port@[1-4]$":
210 properties:
211 reg:
212 minimum: 1
213 maximum: 4
214
215 - if:
216 not:
217 properties:
218 compatible:
219 contains:
220 enum:
221 - ti,j7200-cpswxg-nuss
222 - ti,j721e-cpswxg-nuss
223 - ti,j784s4-cpswxg-nuss
224 then:
225 properties:
226 ethernet-ports:
227 patternProperties:
228 "^port@[3-8]$": false
229 "^port@[1-2]$":
230 properties:
231 reg:
232 minimum: 1
233 maximum: 2
234
235 additionalProperties: false
236
237 examples:
238 - |
239 #include <dt-bindings/soc/ti,sci_pm_domain.h>
240 #include <dt-bindings/net/ti-dp83867.h>
241 #include <dt-bindings/interrupt-controller/irq.h>
242 #include <dt-bindings/interrupt-controller/arm-gic.h>
243
244 bus {
245 #address-cells = <2>;
246 #size-cells = <2>;
247
248 mcu_cpsw: ethernet@46000000 {
249 compatible = "ti,am654-cpsw-nuss";
250 #address-cells = <2>;
251 #size-cells = <2>;
252 reg = <0x0 0x46000000 0x0 0x200000>;
253 reg-names = "cpsw_nuss";
254 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
255 dma-coherent;
256 clocks = <&k3_clks 5 10>;
257 clock-names = "fck";
258 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
261
262 dmas = <&mcu_udmap 0xf000>,
263 <&mcu_udmap 0xf001>,
264 <&mcu_udmap 0xf002>,
265 <&mcu_udmap 0xf003>,
266 <&mcu_udmap 0xf004>,
267 <&mcu_udmap 0xf005>,
268 <&mcu_udmap 0xf006>,
269 <&mcu_udmap 0xf007>,
270 <&mcu_udmap 0x7000>;
271 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
272 "rx";
273
274 ethernet-ports {
275 #address-cells = <1>;
276 #size-cells = <0>;
277
278 cpsw_port1: port@1 {
279 reg = <1>;
280 ti,mac-only;
281 label = "port1";
282 ti,syscon-efuse = <&mcu_conf 0x200>;
283 phys = <&phy_gmii_sel 1>;
284
285 phy-mode = "rgmii-rxid";
286 phy-handle = <&phy0>;
287 };
288 };
289
290 davinci_mdio: mdio@f00 {
291 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
292 reg = <0x0 0xf00 0x0 0x100>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 clocks = <&k3_clks 5 10>;
296 clock-names = "fck";
297 bus_freq = <1000000>;
298
299 phy0: ethernet-phy@0 {
300 reg = <0>;
301 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
302 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
303 };
304 };
305 };
306
307 cpts@3d000 {
308 compatible = "ti,am65-cpts";
309 reg = <0x0 0x3d000 0x0 0x400>;
310 clocks = <&k3_clks 18 2>;
311 clock-names = "cpts";
312 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-names = "cpts";
314 ti,cpts-ext-ts-inputs = <4>;
315 ti,cpts-periodic-outputs = <2>;
316 };
317 };
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