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Linux/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Rockchip internal OTP (One Time Programmable) memory
  8 
  9 maintainers:
 10   - Heiko Stuebner <heiko@sntech.de>
 11 
 12 properties:
 13   compatible:
 14     enum:
 15       - rockchip,px30-otp
 16       - rockchip,rk3308-otp
 17       - rockchip,rk3588-otp
 18 
 19   reg:
 20     maxItems: 1
 21 
 22   clocks:
 23     minItems: 3
 24     maxItems: 4
 25 
 26   clock-names:
 27     minItems: 3
 28     items:
 29       - const: otp
 30       - const: apb_pclk
 31       - const: phy
 32       - const: arb
 33 
 34   resets:
 35     minItems: 1
 36     maxItems: 3
 37 
 38   reset-names:
 39     minItems: 1
 40     maxItems: 3
 41 
 42 required:
 43   - compatible
 44   - reg
 45   - clocks
 46   - clock-names
 47   - resets
 48   - reset-names
 49 
 50 allOf:
 51   - $ref: nvmem.yaml#
 52   - $ref: nvmem-deprecated-cells.yaml#
 53 
 54   - if:
 55       properties:
 56         compatible:
 57           contains:
 58             enum:
 59               - rockchip,px30-otp
 60               - rockchip,rk3308-otp
 61     then:
 62       properties:
 63         clocks:
 64           maxItems: 3
 65         resets:
 66           maxItems: 1
 67         reset-names:
 68           items:
 69             - const: phy
 70 
 71   - if:
 72       properties:
 73         compatible:
 74           contains:
 75             enum:
 76               - rockchip,rk3588-otp
 77     then:
 78       properties:
 79         clocks:
 80           minItems: 4
 81         resets:
 82           minItems: 3
 83         reset-names:
 84           items:
 85             - const: otp
 86             - const: apb
 87             - const: arb
 88 
 89 unevaluatedProperties: false
 90 
 91 examples:
 92   - |
 93     #include <dt-bindings/clock/px30-cru.h>
 94 
 95     soc {
 96         #address-cells = <2>;
 97         #size-cells = <2>;
 98 
 99         otp: efuse@ff290000 {
100             compatible = "rockchip,px30-otp";
101             reg = <0x0 0xff290000 0x0 0x4000>;
102             clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
103                      <&cru PCLK_OTP_PHY>;
104             clock-names = "otp", "apb_pclk", "phy";
105             resets = <&cru SRST_OTP_PHY>;
106             reset-names = "phy";
107             #address-cells = <1>;
108             #size-cells = <1>;
109 
110             cpu_id: id@7 {
111                 reg = <0x07 0x10>;
112             };
113 
114             cpu_leakage: cpu-leakage@17 {
115                 reg = <0x17 0x1>;
116             };
117 
118             performance: performance@1e {
119                 reg = <0x1e 0x1>;
120                 bits = <4 3>;
121             };
122         };
123     };

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