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Linux/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2 # Copyright (C) 2015, 2019, 2024, Intel Corporation
  3 %YAML 1.2
  4 ---
  5 $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
  6 $schema: http://devicetree.org/meta-schemas/core.yaml#
  7 
  8 title: Altera PCIe Root Port
  9 
 10 maintainers:
 11   - Matthew Gerlach <matthew.gerlach@linux.intel.com>
 12 
 13 properties:
 14   compatible:
 15     enum:
 16       - altr,pcie-root-port-1.0
 17       - altr,pcie-root-port-2.0
 18 
 19   reg:
 20     items:
 21       - description: TX slave port region
 22       - description: Control register access region
 23       - description: Hard IP region
 24     minItems: 2
 25 
 26   reg-names:
 27     items:
 28       - const: Txs
 29       - const: Cra
 30       - const: Hip
 31     minItems: 2
 32 
 33   interrupts:
 34     maxItems: 1
 35 
 36   interrupt-controller: true
 37 
 38   interrupt-map-mask:
 39     items:
 40       - const: 0
 41       - const: 0
 42       - const: 0
 43       - const: 7
 44 
 45   interrupt-map:
 46     maxItems: 4
 47 
 48   "#interrupt-cells":
 49     const: 1
 50 
 51   msi-parent: true
 52 
 53 required:
 54   - compatible
 55   - reg
 56   - reg-names
 57   - interrupts
 58   - "#interrupt-cells"
 59   - interrupt-controller
 60   - interrupt-map
 61   - interrupt-map-mask
 62 
 63 allOf:
 64   - $ref: /schemas/pci/pci-host-bridge.yaml#
 65   - if:
 66       properties:
 67         compatible:
 68           enum:
 69             - altr,pcie-root-port-1.0
 70     then:
 71       properties:
 72         reg:
 73           maxItems: 2
 74 
 75         reg-names:
 76           maxItems: 2
 77 
 78     else:
 79       properties:
 80         reg:
 81           minItems: 3
 82 
 83         reg-names:
 84           minItems: 3
 85 
 86 
 87 unevaluatedProperties: false
 88 
 89 examples:
 90   - |
 91     #include <dt-bindings/interrupt-controller/arm-gic.h>
 92     #include <dt-bindings/interrupt-controller/irq.h>
 93     pcie_0: pcie@c00000000 {
 94         compatible = "altr,pcie-root-port-1.0";
 95         reg = <0xc0000000 0x20000000>,
 96               <0xff220000 0x00004000>;
 97         reg-names = "Txs", "Cra";
 98         interrupt-parent = <&hps_0_arm_gic_0>;
 99         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
100         interrupt-controller;
101         #interrupt-cells = <1>;
102         bus-range = <0x0 0xff>;
103         device_type = "pci";
104         msi-parent = <&msi_to_gic_gen_0>;
105         #address-cells = <3>;
106         #size-cells = <2>;
107         interrupt-map-mask = <0 0 0 7>;
108         interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,
109                         <0 0 0 2 &pcie_0 0 0 0 2>,
110                         <0 0 0 3 &pcie_0 0 0 0 3>,
111                         <0 0 0 4 &pcie_0 0 0 0 4>;
112         ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000>,
113                  <0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
114     };

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