1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Amlogic Meson AXG DWC PCIe SoC controller
8
9 maintainers:
10 - Neil Armstrong <neil.armstrong@linaro.org>
11
12 description:
13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
14
15 allOf:
16 - $ref: /schemas/pci/pci-host-bridge.yaml#
17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
18
19 # We need a select here so we don't match all nodes with 'snps,dw-pcie'
20 select:
21 properties:
22 compatible:
23 enum:
24 - amlogic,axg-pcie
25 - amlogic,g12a-pcie
26 required:
27 - compatible
28
29 properties:
30 compatible:
31 items:
32 - enum:
33 - amlogic,axg-pcie
34 - amlogic,g12a-pcie
35 - const: snps,dw-pcie
36
37 reg:
38 items:
39 - description: External local bus interface registers
40 - description: Meson designed configuration registers
41 - description: PCIe configuration space
42
43 reg-names:
44 items:
45 - const: elbi
46 - const: cfg
47 - const: config
48
49 interrupts:
50 maxItems: 1
51
52 clocks:
53 items:
54 - description: PCIe GEN 100M PLL clock
55 - description: PCIe RC clock gate
56 - description: PCIe PHY clock
57
58 clock-names:
59 items:
60 - const: pclk
61 - const: port
62 - const: general
63
64 phys:
65 maxItems: 1
66
67 phy-names:
68 const: pcie
69
70 resets:
71 items:
72 - description: Port Reset
73 - description: Shared APB reset
74
75 reset-names:
76 items:
77 - const: port
78 - const: apb
79
80 num-lanes:
81 const: 1
82
83 power-domains:
84 maxItems: 1
85
86 required:
87 - compatible
88 - reg
89 - reg-names
90 - interrupts
91 - clock
92 - clock-names
93 - "#address-cells"
94 - "#size-cells"
95 - "#interrupt-cells"
96 - interrupt-map
97 - interrupt-map-mask
98 - ranges
99 - bus-range
100 - device_type
101 - num-lanes
102 - phys
103 - phy-names
104 - resets
105 - reset-names
106
107 unevaluatedProperties: false
108
109 examples:
110 - |
111 #include <dt-bindings/interrupt-controller/irq.h>
112 #include <dt-bindings/interrupt-controller/arm-gic.h>
113 pcie: pcie@f9800000 {
114 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
115 reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
116 reg-names = "elbi", "cfg", "config";
117 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
118 clocks = <&pclk>, <&clk_port>, <&clk_phy>;
119 clock-names = "pclk", "port", "general";
120 resets = <&reset_pcie_port>, <&reset_pcie_apb>;
121 reset-names = "port", "apb";
122 phys = <&pcie_phy>;
123 phy-names = "pcie";
124 #interrupt-cells = <1>;
125 interrupt-map-mask = <0 0 0 0>;
126 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
127 bus-range = <0x0 0xff>;
128 #address-cells = <3>;
129 #size-cells = <2>;
130 device_type = "pci";
131 num-lanes = <1>;
132 ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;
133 };
134 ...
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