1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Apple PCIe host controller
8
9 maintainers:
10 - Mark Kettenis <kettenis@openbsd.org>
11
12 description: |
13 The Apple PCIe host controller is a PCIe host controller with
14 multiple root ports present in Apple ARM SoC platforms, including
15 various iPhone and iPad devices and the "Apple Silicon" Macs.
16 The controller incorporates Synopsys DesigWare PCIe logic to
17 implements its root ports. But the ATU found on most DesignWare
18 PCIe host bridges is absent.
19
20 All root ports share a single ECAM space, but separate GPIOs are
21 used to take the PCI devices on those ports out of reset. Therefore
22 the standard "reset-gpios" and "max-link-speed" properties appear on
23 the child nodes that represent the PCI bridges that correspond to
24 the individual root ports.
25
26 MSIs are handled by the PCIe controller and translated into regular
27 interrupts. A range of 32 MSIs is provided. These 32 MSIs can be
28 distributed over the root ports as the OS sees fit by programming
29 the PCIe controller's port registers.
30
31 properties:
32 compatible:
33 items:
34 - enum:
35 - apple,t8103-pcie
36 - apple,t8112-pcie
37 - apple,t6000-pcie
38 - const: apple,pcie
39
40 reg:
41 minItems: 3
42 maxItems: 6
43
44 reg-names:
45 minItems: 3
46 items:
47 - const: config
48 - const: rc
49 - const: port0
50 - const: port1
51 - const: port2
52 - const: port3
53
54 ranges:
55 minItems: 2
56 maxItems: 2
57
58 interrupts:
59 description:
60 Interrupt specifiers, one for each root port.
61 minItems: 1
62 maxItems: 4
63
64 msi-parent: true
65
66 msi-ranges:
67 maxItems: 1
68
69 iommu-map: true
70 iommu-map-mask: true
71
72 power-domains:
73 maxItems: 1
74
75 required:
76 - compatible
77 - reg
78 - reg-names
79 - bus-range
80 - interrupts
81 - msi-controller
82 - msi-parent
83 - msi-ranges
84
85 unevaluatedProperties: false
86
87 allOf:
88 - $ref: /schemas/pci/pci-host-bridge.yaml#
89 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
90 - if:
91 properties:
92 compatible:
93 contains:
94 const: apple,t8103-pcie
95 then:
96 properties:
97 reg:
98 maxItems: 5
99 interrupts:
100 maxItems: 3
101
102 examples:
103 - |
104 #include <dt-bindings/interrupt-controller/apple-aic.h>
105
106 soc {
107 #address-cells = <2>;
108 #size-cells = <2>;
109
110 pcie0: pcie@690000000 {
111 compatible = "apple,t8103-pcie", "apple,pcie";
112 device_type = "pci";
113
114 reg = <0x6 0x90000000 0x0 0x1000000>,
115 <0x6 0x80000000 0x0 0x100000>,
116 <0x6 0x81000000 0x0 0x4000>,
117 <0x6 0x82000000 0x0 0x4000>,
118 <0x6 0x83000000 0x0 0x4000>;
119 reg-names = "config", "rc", "port0", "port1", "port2";
120
121 interrupt-parent = <&aic>;
122 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
123 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
124 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
125
126 msi-controller;
127 msi-parent = <&pcie0>;
128 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
129
130 iommu-map = <0x100 &dart0 1 1>,
131 <0x200 &dart1 1 1>,
132 <0x300 &dart2 1 1>;
133 iommu-map-mask = <0xff00>;
134
135 bus-range = <0 3>;
136 #address-cells = <3>;
137 #size-cells = <2>;
138 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
139 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
140
141 power-domains = <&ps_apcie_gp>;
142 pinctrl-0 = <&pcie_pins>;
143 pinctrl-names = "default";
144
145 pci@0,0 {
146 device_type = "pci";
147 reg = <0x0 0x0 0x0 0x0 0x0>;
148 reset-gpios = <&pinctrl_ap 152 0>;
149
150 #address-cells = <3>;
151 #size-cells = <2>;
152 ranges;
153 };
154
155 pci@1,0 {
156 device_type = "pci";
157 reg = <0x800 0x0 0x0 0x0 0x0>;
158 reset-gpios = <&pinctrl_ap 153 0>;
159
160 #address-cells = <3>;
161 #size-cells = <2>;
162 ranges;
163 };
164
165 pci@2,0 {
166 device_type = "pci";
167 reg = <0x1000 0x0 0x0 0x0 0x0>;
168 reset-gpios = <&pinctrl_ap 33 0>;
169
170 #address-cells = <3>;
171 #size-cells = <2>;
172 ranges;
173 };
174 };
175 };
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